Interface to a memory system for a processor having a replay...

Interrupt branch address formed by concatenation of base address

Interrupt control apparatus and method

Interrupt handling

Interrupt processing system and method for information processin

Interruptable multiple execution unit processing during...

Interruptible and re-entrant cache clean range instruction

Interruptible digital signal processor having two...

Invalidating instructions in fetched instruction blocks upon pre

Isochronous pipelined processor with deterministic control

Jumping to a recombine target address which is encoded in a...

Last iteration loop branch prediction upon counter threshold...

Layered counterflow pipeline processor with anticipatory control

Leading bit prediction with in-parallel correction

Limiting concurrent modification and execution of...

Limiting entries searched in load reorder queue to between...

Linear vector computation

Link and fall-through address formation using a program...

Link pipe system for storage and retrieval of sequences of...

Link stack repair of erroneous speculative update