Interruptible digital signal processor having two...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...

Reexamination Certificate

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C712S229000, C712S233000, C712S035000, C712S043000

Reexamination Certificate

active

07082518

ABSTRACT:
The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.

REFERENCES:
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5115506 (1992-05-01), Cohen et al.
patent: 5717933 (1998-02-01), Mann
patent: 5844422 (1998-12-01), Trimberger et al.
patent: 5860014 (1999-01-01), Cheong et al.
patent: 5987601 (1999-11-01), Donovan
patent: 6026479 (2000-02-01), Fisher et al.
patent: 6128728 (2000-10-01), Dowling

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