Leading bit prediction with in-parallel correction

Details Leading bit prediction with in-parallel correction Leading bit prediction with in-parallel correction

2002-06-10

2004-06-29

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S505000

Reexamination Certificate

active

06757812

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to microprocessors and, more particularly, to a processor architecture employing an improved floating point unit (FPU).
BACKGROUND OF THE INVENTION
The ever-growing requirement for high performance computers demands that computer hardware architectures maximize software performance. Conventional computer architectures are made up of three primary components: (1) a processor, (2) a system memory and (3) one or more input/output devices. The processor controls the system memory and the input/output (“I/O”) devices. The system memory stores not only data, but also instructions that the processor is capable of retrieving and executing to cause the computer to perform one or more desired processes or functions. The I/O devices are operative to interact with a user through a graphical user interface (“GUI”) (such as provided by Microsoft Windows™ or IBM OS/2™), a network portal device, a printer, a mouse or other conventional device for facilitating interaction between the user and the computer.
Over the years, the quest for ever-increasing processing speeds has followed different directions. One approach to improve computer performance is to increase the rate of the clock that drives the processor. As the clock rate increases, however, the processor's power consumption and temperature also increase. Increased power consumption is expensive and high circuit temperatures may damage the processor. Further, the processor clock rate may not increase beyond a threshold physical speed at which signals may traverse the processor. Simply stated, there is a practical maximum to the clock rate that is acceptable to conventional processors.
An alternate approach to improve computer performance is to increase the number of instructions executed per clock cycle by the processor (“processor throughput”). One technique for increasing processor throughput is pipelining, which calls for the processor to be divided into separate processing stages (collectively termed a “pipeline”). Instructions are processed in an “assembly line” fashion in the processing stages. Each processing stage is optimized to perform a particular processing function, thereby causing the processor as a whole to become faster.
“Superpipelining” extends the pipelining concept further by allowing the simultaneous processing of multiple instructions in the pipeline. Consider, as an example, a processor in which each instruction executes in six stages, each stage requiring a single clock cycle to perform its function. Six separate instructions can therefore be processed concurrently in the pipeline; i.e., the processing of one instruction is completed during each clock cycle. The instruction throughput of an n-stage pipelined architecture is therefore, in theory, n times greater than the throughput of a non-pipelined architecture capable of completing only one instruction every n clock cycles.
Another technique for increasing overall processor speed is “superscalar” processing. Superscalar processing calls for multiple instructions to be processed per clock cycle. Assuming that instructions are independent of one another (the execution of each instruction does not depend upon the execution of any other instruction), processor throughput is increased in proportion to the number of instructions processed per clock cycle (“degree of scalability”). If, for example, a particular processor architecture is superscalar to degree three (i.e., three instructions are processed during each clock cycle), the instruction throughput of the processor is theoretically tripled.
These techniques are not mutually exclusive; processors may be both superpipelined and superscalar. However, operation of such processors in practice is often far from ideal, as instructions tend to depend upon one another and are also often not executed efficiently within the pipeline stages. In actual operation, instructions often require varying amounts of processor resources, creating interruptions (“bubbles” or “stalls”) in the flow of instructions through the pipeline. Consequently, while superpipelining and superscalar techniques do increase throughput, the actual throughput of the processor ultimately depends upon the particular instructions processed during a given period of time and the particular implementation of the processor's architecture.
The speed at which a processor can perform a desired task is also a function of the number of instructions required to code the task. A processor may require one or many clock cycles to execute a particular instruction. Thus, in order to enhance the speed at which a processor can perform a desired task, both the number of instructions used to code the task as well as the number of clock cycles required to execute each instruction should be minimized.
Statistically, certain instructions are executed more frequently than others. If the design of a processor is optimized to rapidly process the instructions that occur most frequently, then the overall throughput of the processor can be increased. Unfortunately, the optimization of a processor for certain frequent instructions is usually obtained only at the expense of other less frequent instructions, or requires additional circuitry, which increases the size of the processor.
As computer programs have become increasingly more graphic-oriented processors have had to deal more and more with operations on numbers in floating point notation, one aspect of which involves “normalization”. Performing a floating point mathematical operation and normalizing the result can be a relatively slow and tedious process; after computational circuitry performs a floating point operation on two operands, the result must be normalized so as to contain a “one” in the most significant bit (“MSB”) of the mantissa. A leading zero counter (“LZC”), or leading one detector, is often used to count the number of leading zeros, or detect the bit position of the first one, in the mantissa and the gloating point result is then normalized by shifting the mantissa the number of bits indicated by the LZC. The result must also be converted to a signed magnitude form and rounded to ensure sufficient accuracy and precision; typically, the steps of converting and rounding require two separate passes through an adder circuit.
Both computation and normalization steps can be time consuming; for example, the computation step is delayed due to the carry propagation of data during the floating point operation. In conventional systems, the normalization process does not begin until after the floating point operation is complete; for example, see U.S. Pat. No. 5,633,819 to Brashears, et. al. issued May 27, 1997. Thus, conventional FPUs are inherently slow since the computation and normalization steps must be performed sequentially.
Several approaches have been developed to decrease the time required for the computation and normalization of numbers associated with floating point mathematical operations. One such approach employs leading-zero anticipatory logic, such as that disclosed by Suzuki, et al., in “Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 8, August 1996, or Hokenek and Montoye in “Leading-zero Anticipator (LZA) in the IBM RISC System/6000 Floating-point Execution Unit”, IBM J. Res. Develop., Vol. 34, No. 1, January 1990, or as described in U.S. Pat. Nos. 5,144,570 and 5,040,138, all of which are incorporated herein by reference. Although the LZA approach can be used to minimize the time required for computation and normalization, the LZA approach has the possibility of anticipating wrongly, requiring a correction step. Circuits and methods have been proposed for correcting a wrongly anticipated leading bit; such approaches, however, have heretofore increased the time required for the normalization of numbers associated with floating point mathematical operations.
Therefore, what is needed in the art is a system and method for correcting a leading

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