Interface to a memory system for a processor having a replay...

Details Interface to a memory system for a processor having a replay... Interface to a memory system for a processor having a replay...

2006-08-08

2006-08-08

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S219000

Reexamination Certificate

active

07089409

ABSTRACT:
A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

REFERENCES:
patent: 5012403 (1991-04-01), Keller et al.
patent: 5421022 (1995-05-01), McKeen et al.
patent: 5619662 (1997-04-01), Steely et al.

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