Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Patent
1998-07-28
2000-07-04
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
712 23, 712210, 712201, 710 29, 710 20, G06F 938, G06F 928, G06F 1340
Patent
active
060853166
ABSTRACT:
A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
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Rolf Ernst, "Long Pipelines in Single-Chip Digital Signal Processors--Concepts and Case Study", IEEE Transactions on Circuits and Systems, No. 1 (1991):100-108.
Coates William S.
Jones Ian W.
Lexau Jon
Molnar, deceased Charles E.
Sutherland Ivan E.
Pan Daniel H.
Sun Microsystems Inc.
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