Computer processor with instruction-specific schedulers

Data processing apparatus and method for reducing issue...

Data processing control system, controller, data processing...

Data processing device with instruction controlled clock speed

Data processor for processing a complex instruction by dividing

Decoding instructions for trace cache resume state in system...

Delay slot handling in a processor

Dependency tracking for enabling successive processor...

Dynamic allocation of resources in multiple microprocessor...

Dynamic pipe staging adder

Efficient instruction scheduling with lossy tracking of...

Executing multiple instructions in multi-pipelined processor...

Fast lock-free post-wait synchronization for exploiting...

Fetch and dispatch disassociation apparatus for...

Fetch and dispatch disassociation apparatus for...

Fetch and dispatch disassociation apparatus for...

Fetching and handling a bundle of instructions comprising instru

Fetching instructions to instruction buffer for simultaneous...

Fine grained multi-thread dispatch block mechanism

Grouping logic circuit in a pipelined superscalar processor