Fetch and dispatch disassociation apparatus for...

Details Fetch and dispatch disassociation apparatus for... Fetch and dispatch disassociation apparatus for...

2008-07-15

2009-12-22

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S205000

Reexamination Certificate

active

07636836

ABSTRACT:
A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.

REFERENCES:
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4916652 (1990-04-01), Schwarz et al.
patent: 4924376 (1990-05-01), Ooi
patent: 5313600 (1994-05-01), Kasai
patent: 5404469 (1995-04-01), Chung et al.
patent: 5430851 (1995-07-01), Hirata et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5699537 (1997-12-01), Sharangpani et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5742782 (1998-04-01), Ito et al.
patent: 5745725 (1998-04-01), Simpson
patent: 5745778 (1998-04-01), Alfieri
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5848268 (1998-12-01), Matsuo
patent: 5900025 (1999-05-01), Sollars
patent: 5907702 (1999-05-01), Flynn et al.
patent: 5913049 (1999-06-01), Shiell et al.
patent: 5933627 (1999-08-01), Parady
patent: 6092175 (2000-07-01), Levy et al.
patent: 6105053 (2000-08-01), Kimmel et al.
patent: 6105127 (2000-08-01), Kimura et al.
patent: 6141746 (2000-10-01), Kawano et al.
patent: 6219780 (2001-04-01), Lipasti
patent: 6343348 (2002-01-01), Tremblay et al.
patent: 6378063 (2002-04-01), Corwin et al.
patent: 6460130 (2002-10-01), Trull et al.
patent: 6470443 (2002-10-01), Emer et al.
patent: 6530042 (2003-03-01), Davidson et al.
patent: 6542987 (2003-04-01), Fischer et al.
patent: 6542991 (2003-04-01), Joy et al.
patent: 6622240 (2003-09-01), Olson et al.
patent: 6691221 (2004-02-01), Joshi et al.
patent: 6968444 (2005-11-01), Kroesche et al.
patent: 7035998 (2006-04-01), Nemirovsky et al.
patent: 7046677 (2006-05-01), Monta et al.
patent: 7139898 (2006-11-01), Nemirovsky et al.
patent: 7406586 (2008-07-01), Nemirovsky et al.
Hirata, H. etal., An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads, 1992, ACM pp. 136-145.
Diefendorff, Keith. “WinChip4 Thumbs Nose at ILP.” Microprocessor Report, http://www.mdronline.com/mpr/h/19981207/121605.html, Dec. 7, 1998.
Diefendorff, Keith. “Compaq Chooses SMT for Alpha.” Microprocessor Report, http://www.mdronline.com/mpr/h/19991206/1131601.html Dec. 6, 1999.
Diefendorff, Keith. “Jalapeno Powers Cyrix's M3.” Microprocessor Report. http://www.mdronline.com/mpr/h/19981116/121507.html, Nov. 16, 1998.
Eggers et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors.” Sep. 1998, pp. 12-19, IEEE Micro.
Michael Slater. “Rise Joins x86 Fray with mP6.” Microprocessor Report. http:/www.mdronline.com/mpr/h/19981116/121501/html. Nov. 16, 1998.
Becker et al. The PowerPC 601 Microprocessor, Oct. 1993. pp. 54-68. IEEE Micro.
The PowerPC Architecture: A Specificaiton for a New Family of RISC Processors. Second Edition, Morgan Kaufmann. San Francisco. pp. 70-72. (May 1994).
MC68020 32-Bit Microprocessor User's Manual. Third Edition. Prentice Hall, New Jersey. pp. 3-125, 3-126, and 3-127 (1989).
M.J. Potel, “Real-Time Playback in Animation Systems.” Proceedings of the 4th Annual Conference on Computer Graphis and Interactive Techniques, San Jose, CA. pp. 72-77 (1977).
ARM Archictecture Reference Manual. Prentice Hall. pp. 3-41, 3-42, 3-43, 3-67, 3-68 (1996).
ESA/390 Principles of Operation. IBM Library Server, Table of Contents and Para.7.5.31 and 7.5.70 (1993). (available at http://publibz.boulder.ibm.com/cgi-bin/bookmgr—OS390/BOOK/DZ9AR001/CCONTENTS).
MC88110 Second Generation RISC Microprocessor User's Manual. Motorola, Inc., pp. 10-66, 10-67 and 10-71 (1991).
Diefendorff, Keith et al. “Organization of the Motorola 88110 Superscalar RISC Microprocessor.”IEEE Micro. vol. 12, No. 2, pp. 40-63 (1992).
Kane, Gerry.PA-RISC 2.0 Architecture. Prentice Hall, New Jersey. pp. 7-106 and 7-107 (1996).
Diefendorff, Keith et al. “AltiVec Extension to PowerPC Accelerates Media Processing.”IEEE Micro. vol. 20, No. 2, pp. 85-95 (Mar.-Apr. 2000).
Gwennap, Linley. “Digital 21264 Sets New Standard.”Microprocessor Report. vol. 20, No. 14. 11 Pages (Oct. 28, 1999).
Diefendorff, Keith. “Power4 Focuses on Memory Bandwidth.”Microprocessor Report. vol. 13, No. 13, 13 pages (Oct. 6, 1999).
Diefendorff, Keith. “K7 Challenges Intel.”Microprocessor Report. vol. 12, No. 14, 7 pages (Oct. 26, 1998).

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