Decoding instructions for trace cache resume state in system...

Details Decoding instructions for trace cache resume state in system... Decoding instructions for trace cache resume state in system...

2007-02-20

2007-02-20

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

C711S118000, C712S205000, C712S233000

Reexamination Certificate

active

11217707

ABSTRACT:
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

REFERENCES:
patent: 6055630 (2000-04-01), D'Sa et al.
patent: 6076144 (2000-06-01), Peled et al.
patent: 6453411 (2002-09-01), Hsu et al.
patent: 6721866 (2004-04-01), Roussel et al.

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