Grouping logic circuit in a pipelined superscalar processor

Details Grouping logic circuit in a pipelined superscalar processor Grouping logic circuit in a pipelined superscalar processor

1996-06-11

1999-09-28

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712217, 712209, 712213, 714 39, G06F 938

Patent

active

059580429

ABSTRACT:
A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.

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Hayes (Computer architecture and organization) McGraw-Hill pp. 592-622, Jun. 1988.

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