Dynamic pipe staging adder

Details Dynamic pipe staging adder Dynamic pipe staging adder

1995-11-16

2003-05-06

Follansbee, John A. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S216000

Reexamination Certificate

active

06560695

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to systems for processing information and in particular to an improved method and apparatus for executing instructions. Still more particularly, the present invention relates to an improved method and system for executing instructions requiring different lengths of time for execution.
2. Description of the Related Art
A superscalar microprocessor allows for the out-of-order execution of instructions. In such a microprocessor, a buffer called a “reservation station” is employed to place op codes and operands prior to being sent to an execution unit. In this type of microprocessor instructions are sent to the execution unit when a determination is made that all of the operands are available. Instructions are not required to be executed in program order in such a microprocessor system. Whenever an instruction has all its operands ready, the instruction is selected to be sent for execution by the reservation station. Once the instruction is sent to the execution unit, the reservation station replaces that instruction with the next instruction that is to be sent to the execution unit.
Instructions are sent to an execution unit by asserting a valid signal. The execution unit starts executing the instruction while the reservation station searches for another instruction to send to the execution unit.
In presently available microprocessor systems the execution of instructions in a microprocessor is performed by allocating a selected number of processor cycles for an execution unit to execute a given instruction, whether or not that instruction requires the setting of condition codes. As a result, an instruction that does not require the setting of a condition code has more time allocated for its execution then is necessary. Consequently, excess processor cycles are present to execute many instructions. It would be advantageous to have a method and apparatus for adjusting the amount of time set aside for execution of instructions based on the amount of time required by a particular instruction.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved system for processing information.
It is another object of the present invention to provide a method and system for executing instructions.
It is yet another object of the present invention to provide a method and system for executing instructions requiring different lengths of time for execution.
The present invention provides a method and apparatus for processing instructions in which the time allowed for the execution of an instruction is dynamically allocated. The allocation of time for execution of instruction occurs after the instruction is sent to the execution unit. The execution unit determines whether it can complete the instruction during the current processor cycle. In response to an inability to complete the instruction within the current processor cycle, the execution unit issues a busy signal to the reservation station. The reservation station continues to hold the next instruction until the execution unit is capable of processing it.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 5127093 (1992-06-01), Moore, Jr.
patent: 5185872 (1993-02-01), Arnold et al.
patent: 5432918 (1995-07-01), Stamm
patent: 5524260 (1996-06-01), Matsuda
patent: 5553291 (1996-09-01), Tanaka et al.
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5621910 (1997-04-01), Nagamatsu
patent: 5634026 (1997-05-01), Heaslip et al.

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