Efficient instruction scheduling with lossy tracking of...

Details Efficient instruction scheduling with lossy tracking of... Efficient instruction scheduling with lossy tracking of...

2006-10-31

2006-10-31

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S217000

Reexamination Certificate

active

07130990

ABSTRACT:
A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

REFERENCES:
patent: 2003/0140216 (2003-07-01), Stark et al.
Sato, T. “A simulation of pipelining and decoupling a dynamic instruction scheduling mechanism.” EUROMICRO Conference, 1999. Proceedings. 25th.
Black, Bryan, Application for US Letters Patent for “Hierarchical Scheduling Windows”, U.S. Appl. No. 10/261,578, filed Sep. 30, 2002.
Brekelbaum et al., “Hierarchical Scheduling Windows”, Proc. 35th ACM/IEEE Int'l Symposium on Microarchitecture, 2002, pp. 27-36.
Sato et al., “Revisiting Direct Tag Search Algorithm on Superscalar Processors”. Proc. 29th Ann. Int'l Symposium on Computer Archiecture, pp. 318-329, May 2002.

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