Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2006-03-31
2009-08-04
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C717S150000
Reexamination Certificate
active
07571301
ABSTRACT:
A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce an order of execution, an array to track code completion that is indexed by a modulus of a positive integer number, and/or a set of arrays to track a last code completed by a thread and a current code being executed by a thread.
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Banerjee Utpal
Girkar Milind
Kejariwal Arun
Li Wei
Saito Hideki
Blakely , Sokoloff, Taylor & Zafman LLP
Coleman Eric
Intel Corporation
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