Computer processor with instruction-specific schedulers

Details Computer processor with instruction-specific schedulers Computer processor with instruction-specific schedulers

1998-07-31

2001-10-16

An, Meng-Al T. (Department: 2154)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C712S023000, C712S214000, C712S216000, C712S217000

Reexamination Certificate

active

06304953

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to a computer processor. More particularly, the present invention is directed to a computer processor with instruction-specific schedulers.
BACKGROUND OF THE INVENTION
The primary function of most computer processors is to execute computer instructions. Most processors execute instructions in the programmed order that they are received. However, some recent processors, such as the Pentium® II processor from Intel Corp., are “out-of-order” processors. An out-of-order processor can execute instructions in any order possible as the data and execution units required for each instruction becomes available. Therefore, with an out-of-order processor, execution units within the processor that otherwise may be idle can be more efficiently utilized.
The typical out-of-order processor includes a scheduler. The scheduler determines, for each instruction, when the appropriate execution unit and necessary data items for the instruction are available. When they are available, the scheduler schedules, or dispatches, the instructions.
Most known processors include a single general purpose scheduler that schedules all types of instructions. For example, the Pentium® II processor includes a single Reservation Station (“RS”) that functions as a scheduler. The RS is a twenty instruction queue, and can schedule the instructions in any order. However, in addition to determining the availability of execution units and data items, the RS must track dependencies between instructions, and the latency of the instructions. For example, a second instruction that is dependent on a first instruction cannot be scheduled by the RS until the first instruction has been allowed to execute. The latency of the first instruction indicates the earliest time that the second instruction can be dispatched. Therefore, if the first instruction has a latency of four clock cycles, the RS cannot dispatch the second dependent instruction until at least four cycles after the first instruction was dispatched.
As the speed requirements of processors increase, known schedulers require more and more complex logic to properly schedule instructions. However, the added complexity can introduce undesirable delays in the processor.
Based on the foregoing, there is a need for a processor with a faster and more efficient scheduler than is found in the prior art.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the first scheduler and adapted to dispatch a second type of computer instructions.


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Gurindar S. Sohi, Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers, IEEE Transactions on Computers, vol. 39, No. 3, Mar. 1990, pp. 349-359.

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