Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2008-04-29
2008-04-29
Li, Aimee J. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S219000
Reexamination Certificate
active
10664384
ABSTRACT:
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
REFERENCES:
patent: 5404469 (1995-04-01), Chung et al.
patent: 5555432 (1996-09-01), Hinton et al.
patent: 5574939 (1996-11-01), Keckler et al.
patent: 5742782 (1998-04-01), Ito et al.
patent: 5809325 (1998-09-01), Hinton et al.
patent: 5842036 (1998-11-01), Hinton et al.
patent: 5848256 (1998-12-01), Call et al.
patent: 5864341 (1999-01-01), Hicks et al.
patent: 5870580 (1999-02-01), Walker
patent: 5872947 (1999-02-01), Narayan
patent: 5923862 (1999-07-01), Nguyen et al.
patent: 5933627 (1999-08-01), Parady
patent: 5958041 (1999-09-01), Petolino, Jr. et al.
patent: 5964867 (1999-10-01), Anderson et al.
patent: 6144982 (2000-11-01), Penwar
patent: 6360315 (2002-03-01), Potter
patent: 6393550 (2002-05-01), Fetterman et al.
patent: 6442678 (2002-08-01), Arora
patent: 6601162 (2003-07-01), Teruyama
patent: 6820173 (2004-11-01), Bittel et al.
patent: 6907520 (2005-06-01), Parady
patent: 2003/0182536 (2003-09-01), Teruyama
Swanson, Steven; McDowell, Luke K.; Switft, Michael M.; Eggers, Susan J.; and Levy, Henry M. “An Evaluation of Speculative Instruction Execution on Simultaneous Multithreaded Processors”, ACM Transactions on Computer Systems, © Aug. 2003. pp. 314-340.
Loikkanen, Mat and Bagherzadeh, Nader. “A Fine-Grain Multithreading Superscalar Architecture”, IEEE, © 1996. pp.163-168.
Brutscher, Martin and Zorn, Benjamin G. “Prediction Outcome History-based Confidence Estimation for Load Value Prediction” Journal of Instruction-Level Parallelism 1, © 1999.
Heuring, Vincent P. and Jordan, Harry F. “Computer Systems Design and Architecture”. Reading, Massachusetts: Addison Wesley Longman, Inc., © 1997. pp. 200-202 and 209.
Rosenberg, Jerry M. “Dictionary of Computers, Information Processing, and Telecommunications”. Second Edition. New York: John Wiley & Sons, © 1987. p. 66, term “buffer (BUF)”.
Augsburg Victor Roberts
Bridges Jeffrey Todd
McIlvaine Michael Scott
Sartorius Thomas Andrew
Smith Rodney Wayne
Cockburn Joscelyn G.
Li Aimee J.
Skarsten James O.
Yee Duke W.
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