Select-free dynamic instruction scheduling

Details Select-free dynamic instruction scheduling Select-free dynamic instruction scheduling

2006-01-17

2006-01-17

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

Reexamination Certificate

active

06988185

ABSTRACT:
A processor having select-free scheduling separates the wakeup and select logic into two loops. A wakeup loop holds scheduler instructions including unexecuted instructions, and indicates which of the unexecuted instructions may be ready to be executed. At least one of the unexecuted instructions is to wakeup and notify at least another of the unexecuted instructions to speculatively wakeup. A select loop selects at least one of the indicated ready instructions for execution.

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