Speculative scheduling of instructions with source operand...

Details Speculative scheduling of instructions with source operand... Speculative scheduling of instructions with source operand...

2005-08-02

2005-08-02

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S023000, C712S217000, C712S218000

Reexamination Certificate

active

06925550

ABSTRACT:
A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

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