Electrical computers and digital processing systems: processing – Instruction issuing
Reexamination Certificate
2008-04-29
2008-04-29
Li, Aimee J. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
C712S219000
Reexamination Certificate
active
07366877
ABSTRACT:
A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic speculatively issues instructions from a given thread based on the probability that the required operands will be available when the instruction reaches the stage in the pipeline where they are required. Issue of an instruction is blocked if the current pipeline conditions indicate that there is a significant probability that the instruction will need to stall in a shared resource to wait for operands. Once the probability that the instruction will stall is below a certain threshold, based on current pipeline conditions, the instruction is allowed to issue.
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Augsburg Victor Roberts
Bridges Jeffrey Todd
McIlvaine Michael Scott
Sartorius Thomas Andrew
Smith Rodney Wayne
Cockburn Joscelyn G.
International Business Machines - Corporation
Li Aimee J.
Skarsten James O.
Yee Duke W.
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