Stall optimization for an in-order, multi-stage processor...

Electrical computers and digital processing systems: processing – Instruction issuing

Reexamination Certificate

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C712S212000, C712S219000

Reexamination Certificate

active

10419360

ABSTRACT:
According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.

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patent: 5404552 (1995-04-01), Ikenaga
patent: 5860018 (1999-01-01), Panwar
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6163840 (2000-12-01), Chrysos et al.
patent: 6341324 (2002-01-01), Caulk et al.
patent: 2001/0007125 (2001-07-01), Cofler et al.

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