Stall optimization for an in-order, multi-stage processor...

Details Stall optimization for an in-order, multi-stage processor... Stall optimization for an in-order, multi-stage processor...

2007-07-10

2007-07-10

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction issuing

C712S212000, C712S219000

Reexamination Certificate

active

10419360

ABSTRACT:
According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.

REFERENCES:
patent: 5133069 (1992-07-01), Asato et al.
patent: 5325495 (1994-06-01), McLellan
patent: 5404552 (1995-04-01), Ikenaga
patent: 5860018 (1999-01-01), Panwar
patent: 6035422 (2000-03-01), Hohl et al.
patent: 6163840 (2000-12-01), Chrysos et al.
patent: 6341324 (2002-01-01), Caulk et al.
patent: 2001/0007125 (2001-07-01), Cofler et al.

Affiliated with

Also associated with

Rating

Stall optimization for an in-order, multi-stage processor... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stall optimization for an in-order, multi-stage processor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stall optimization for an in-order, multi-stage processor... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3773158