Identifying execution ready instructions and allocating...
Information processing system and information processing method
Inhibiting of a co-issuing instruction in a processor having...
Instruction alignment unit employing dual instruction queues for
Instruction buffer and method of controlling the instruction...
Instruction cache association crossbar switch
Instruction cache associative crossbar switch
Instruction control device and method therefor
Instruction decoder/dispatch
Instruction grouping history on fetch-side dispatch group...
Line-oriented reorder buffer configured to selectively store...
Loading previously dispatched slots in multiple instruction...
Management of both renamed and architected registers in a supers
Mechanism for self-initiated instruction issuing and method...
Method and apparatus for constructing a pre-scheduled...
Method and apparatus for controlling an instruction pipeline in
Method and apparatus for controlling an instruction pipeline...
Method and apparatus for dispatching instructions to execution u
Method and apparatus for distributing commands to a...
Method and apparatus for dual issue of program instructions to s