Apparatus and method for adjusting instruction thread...

Apparatus and method for adjusting instruction thread...

Apparatus and method for realizing effective parallel...

Circuit and method for instruction compression and dispersal...

Circuit arrangement and method of dispatching instructions...

Clustering stream and/or instruction queues for...

Computer architecture capable of execution of general...

Computer processor with instruction-specific schedulers

Data processor for processing a complex instruction by dividing

Dynamic allocation of resources in multiple microprocessor...

Executing multiple instructions in multi-pipelined processor...

Fast lock-free post-wait synchronization for exploiting...

Fetch and dispatch disassociation apparatus for...

Fetch and dispatch disassociation apparatus for...

Fetch and dispatch disassociation apparatus for...

Fetching and handling a bundle of instructions comprising instru

Fetching instructions to instruction buffer for simultaneous...

Grouping logic circuit in a pipelined superscalar processor

Guard bits in a VLIW instruction control routing of operations t

Identification bit at a predetermined instruction location...