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Partitioned issue queue and allocation strategy

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Pipe scheduling for pipelines based on destination register...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Pipelined instruction dispatch unit in a superscalar processor

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Pipelined instruction dispatch unit in a superscalar processor

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reissue Patent

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Pre-steering register renamed instructions to execution unit...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Predecoding and steering mechanism for instructions in a supersc

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Preventing the execution of a set of instructions in...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Processor

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Processor

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Processor architecture including grouping circuit

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Processor for making more efficient use of idling components...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Processor to execute in parallel plurality of instructions...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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