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Changing instruction set architecture mode by comparison of...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Coding standard token in a system compromising a plurality of pi

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Command protocol for integrated circuits

Electrical computers and digital processing systems: processing – Instruction decoding
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Compressed string and multiple generation engine

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Compressing variable-length instruction prefix bytes

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Compression of processor instructions

Electrical computers and digital processing systems: processing – Instruction decoding
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Compression of program instructions using advanced...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Computation core executing multiple operation DSP...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Computer for execution of RISC and CISC instruction sets

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Computer instruction compression

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Computer instructions for having extended signed...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Computer processor system for executing RXE format floating poin

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Conditional instruction execution via emissary instruction...

Electrical computers and digital processing systems: processing – Instruction decoding
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Configuration control within data processing systems

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Constant reconstructing processor which supports reductions...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Constant reconstruction processor that supports reductions...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
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Control forwarding in a pipeline digital processor

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Converting program-specific virtual machine instructions...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Data processing apparatus and method for handling...

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Data processing apparatus and method for handling...

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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