Compressed string and multiple generation engine

Details Compressed string and multiple generation engine Compressed string and multiple generation engine

1999-07-29

2002-08-27

Treat, William M. (Department: 2783)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S211000, C712S225000, C712S241000

Reexamination Certificate

active

06442675

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and in particular to a processor in a data processing system. More particularly, the present invention relates to processing string and multiple load/store instructions.
2. Description of the Related Art
String instructions are data structures that consist of “multiples,” which are instructions that are subsets of string instructions. The multiples' size is measured in half word, word or word lengths and typically, the multiples within the string require sequencing for appropriate processing. String instructions, as a whole, present a problem for Reduced instruction set computer (“RISC”) processors. Because of the architecture, RISC processors utilize a relatively small set of fundamental instructions and repeat that set of instructions at a high clock frequency. Though RISC processors process only a limited set of fundamental instructions (hereinafter referred to as elements), string instructions, which have varying lengths, are comprised of multiple fundamental instructions and must be broken down to the fundamentals and processed sequentially by the RISC processor.
RISC processors are employed in many data processing systems and are generally characterized by high throughput of instructions. RISC processors usually operate at a high clock frequency and because of the minimal instruction set do so very efficiently. In addition to high clock speed, processor efficiency is improved even more by the inclusion of multiple execution units allowing the execution of two, and sometimes more, instructions per clock cycle. RISC processors are frequently employed as core processing “engines” to larger more complex processors.
Processors with the ability to execute multiple instructions per clock cycle are described as “superscalar.” Superscalar processors, such as the PowerPC™ family of processors available from IBM Corporation of Armonk, N.Y., provide simultaneous dispatch of multiple instructions. Included in the processor are an Instruction Cache (“IC”), an Instruction Dispatch Unit (“IDU”), an Execution Unit (“EU”) and a Completion Unit (“CU”). Generally, a superscalar, RISC processor is “pipelined,” meaning that a second instruction is waiting to enter the execution unit as soon as the previous instruction is finished.
In a superscalar processor, instruction processing is usually accomplished in six stages—fetch, decode, dispatch, execute, writeback and completion. The fetch stage is primarily responsible for fetching instructions from the instruction cache and determining the address of the next instruction to be fetched. The decode stage generally handles all time-critical instruction decoding for instructions in the instruction buffer. The dispatch stage is responsible for non-time-critical decoding of instructions supplied by the decode stage and for determining which of the instructions can be dispatched in the current cycle.
The execute stage executes the instruction selected in the dispatch stage, which may come from the reservation stations or from instructions arriving from dispatch. The completion stage maintains the correct architectural machine state by considering instructions residing in the completion buffer and utilizing information about the status of instructions provided by the execute stage. The write back stage is used to write back-any information from the rename buffers that is not written back by the completion stage.
A processor utilizing a RISC processor core is restricted by the limitations of a RISC processor; i.e. minimal instruction length and limited instruction set. The RISC processor core requires that strings and multiples be broken down into a series of simple load or store operations. The RISC processor handles variable length string and multiple load/store instructions by routing each string instruction to the functional unit that executes it, i.e., a load store unit, and the functional unit has to internally recognize this as a string instruction. A problem with this method is the instruction is sequentially executed through a single functional (i.e., load/store) unit, even though there are multiple functional units in a RISC processor. The functional unit must internally break the instruction into smaller instructions before executing each instruction sequentially.
It would be desirable therefore, to provide a method and apparatus that would increase the speed of handling variable length streams of string instructions.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and system that allows for variable length streams of load or store instructions in a RISC processor.
It is another object of the present invention to provide a method and system for converting variable length instructions-into operations usable by a RISC processor.
The foregoing objects are achieved as is now described. A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the functions contained in the string instruction. The functions that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the functions in the string instruction and whether or not instructions (internal operations) need to be generated.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 4875160 (1989-10-01), Brown, III
patent: 5341482 (1994-08-01), Cutler et al.
patent: 5440703 (1995-08-01), Ray et al.
patent: 5481693 (1996-01-01), Blomgren et al.
patent: 5606696 (1997-02-01), Ackerman et al.
patent: 5717946 (1998-02-01), Satou et al.
patent: 5721867 (1998-02-01), Kuttanna et al.
patent: 5794063 (1998-08-01), Favor
patent: 6055625 (2000-04-01), Nakada et al.
patent: 6070238 (2000-05-01), Feiste et al.
patent: 6128722 (2000-10-01), Fry et al.
U.S. patent application Ser. No. 09/345,161, Derrick et al., filed Jun. 29, 1999.
U.S. patent application Ser. No. 09/354,498, Derrick et al., filed Jul. 16, 1999.
U.S. patent application Ser. No. 09/363,463, Kahle et al., filed Jul. 29, 1999.
IBM Technical Disclosure Bulletin, Jun. 1992, IBM, NN9206345, vol. 35, Issue No. 1B, pp. 345-347.
IBM Technical Disclosure Bulletin, Jan. 1993, IBM, NN9301395, vol. 36, Issue No. 1, pp. 395-396.

Affiliated with

Also associated with

Rating

Compressed string and multiple generation engine does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compressed string and multiple generation engine, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compressed string and multiple generation engine will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2912475