Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Reexamination Certificate
1998-07-29
2001-03-27
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
C712S024000
Reexamination Certificate
active
06209080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessors and is a technique for making effective use of redundant and unused areas that are present within instructions and for enabling faster processing when a program is executed.
2. Description of the Prior Art
In recent years, increases in processing capability and processing speed of appliances using embedded microprocessors have led to an increasing demand for microprocessors (hereinafter simply referred to as “processors”) that can execute programs with high code efficiency. This means that it is preferable for there to be no redundant areas or unused areas in the instructions that compose a program.
In particular, when using fixed length instructions, such as VLIW (Very Long Instruction Words), there are cases when it is necessary to insert redundant codes, such as no-operation codes (“nop” codes), into instructions. VLIW are composed of a plurality of operation fields, with each operation field specifying an operation that corresponds to one of a plurality of operation units provided within a processor. Due to interdependencies between operations, however, it is not always possible to process a plurality of operations using parallel processing.
One conventional method of avoiding the decreases in code efficiency that accompany the insertion of “nop” codes is the VLIW-type computer system disclosed by Japanese Laid-Open Patent Application H08-161169.
FIG. 1
shows the instruction format used in the above technique.
As shown in
FIG. 1
, when a “nop” code needs to be inserted into a field in which Instruction #2 should be stored, (hereinafter “Operation Field #2) this technique inserts a constant that is to be used by a different operation in place of the “nop” code into operation field #2 and inserts instruction validation information into one part of a field in which instruction #1 should be stored to show that the constant has been inserted. When executing this instruction, a processor first refers to the instruction validation information and so determines that only a constant is present in operation field #2. The processor then uses this constant as the operand of an operation. In this way, the existence of redundant areas within instructions due to the insertion of “nop” codes can be avoided.
The above technique, however, has a drawback in that the size of the constants that can be inserted into the redundant areas is limited.
As one example, when it is necessary to insert a “nop” code into a 32-bit operation field, it is not possible to insert any part of a 64-bit constant. Similarly, when there is an unused 8-bit area in a fixed 32-bit instruction, it is only possible to use the unused area when inserting a constant that is 8 bits long or shorter. In this case, it is not possible to insert an absolute address that is expressed using 32 bits.
While the above technique may be effective when there is a relatively large redundant area in an instruction, when instructions have a relatively short length, such as 32 bits, any redundant area in the instructions will naturally be short, preventing the insertion of constants into a large saw number of redundant areas when using the above technique. This constitutes a major problem.
SUMMARY OF THE INVENTION
The present invention was conceived in view of the stated problems and has a primary object of providing a processor that can make effective use of redundant areas in instructions that are not conventionally used while at the same time making programming easier. The second object of the present invention is to provide a processor capable of faster processing.
The first object of the present invention can be achieved by a processor for executing operations based on instructions, the processor including: an instruction register for storing an instruction; a first constant storage unit including a first storage area; a second constant storage unit including a second storage area; a decoding unit for decoding the instruction stored in the instruction register and for giving an indication of one of the following four cases—(1) a first case where the it instruction includes a first constant to be stored into the first constant storage unit, (2) a second case where the instruction includes a second constant to be stored into the second constant storage unit, (3) a third case where a constant stored in the first constant storage unit is to be used in an operation, and (4) a fourth case where a constant stored in the second constant storage unit is to be used in an operation; a constant transfer unit for operating as follows—(a) when the decoding unit indicates the first case and no valid constant is stored in the first constant storage unit, the constant transfer unit transfers the first constant from the instruction register to the first constant storage unit and sets the transferred first constant in the first constant storage unit as a valid constant, (b) when the decoding unit indicates the first case and a valid constant is stored in the first constant storage unit, the constant transfer unit transfers the first constant from the instruction register to the first constant storage unit so as to retain the valid constant, links the first constant and the valid constant in the first constant storage unit, and sets a linking result as a new valid constant, and (c) when the decoding unit indicates the second case and no valid constant is stored in the second constant storage unit, the constant transfer unit transfers the second constant from the instruction register to the second constant storage unit and sets the transferred second constant in the second constant storage unit as a valid constant, (d) when the decoding unit indicates the second case and a valid constant is stored in the second constant storage unit, the constant transfer unit transfers the second constant from the instruction register to the second constant storage unit so as to retain the valid constant, links the second constant and the valid constant in the second constant storage unit, and sets a linking result as a new valid constant; and an execution unit for operating as follows—(i) when the decoding unit indicates the third case, the execution unit reads the constant stored in the first constant storage unit and executes the operation using the read constant as an operand, and (ii) when the decoding unit indicates the fourth case, the execution unit reads the constant stored in the second constant storage unit and executes the operation using the read constant as an operand.
By doing so, pieces of two constants of different types that are distributed across a plurality of instructions can be respectively accumulated in the first constant storage unit and in the second constant storage unit, thereby restoring the two original constants. By accumulating two constants in parallel, a large decrease can be made in the number of “nop” codes that need to be inserted into a program. As a result, programs for the present processor have a smaller code size and require fewer execution cycles. Programming is also much easier.
Here, the decoding unit may indicate one of the third case and the fourth case based on an operation code for an operation that is included in the instruction in the instruction register.
By doing so, the constant storage unit that is to be used can be decided according to the type of processing to be performed, making programming easier.
Here, the decoding unit may indicate the third case when an operation code shows a branch operation and the fourth case when an operation code shows an arithmetic logic operation, the first constant storage unit being provided specially for branch operations and the second constant storage unit being provided for arithmetic logic operations.
By doing so, different constants can be stored in a first constant storage unit for branching operations and a second constant storage unit for arithmetic logic operations. This also makes programming easier.
Here, in the first case, the constant transfer un
Heishi Taketo
Higaki Nobuo
Miyaji Shinya
Odani Kensuke
Takayama Shuichi
An Meng-Al T.
Chiang Jungwon
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
LandOfFree
Constant reconstruction processor that supports reductions... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Constant reconstruction processor that supports reductions..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Constant reconstruction processor that supports reductions... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2441870