Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-05-12
2004-11-16
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S032000, C712S035000, C712S200000
Reexamination Certificate
active
06820189
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to digital signal processors and, more particularly, to computational core architectures that facilitate both complex digital signal processing computations and microcontroller operations.
BACKGROUND OF THE INVENTION
A digital signal computer, or digital signal processor (DSP), is a special purpose computer that is designed to optimize performance for digital signal processing applications, such as, for example, Fast Fourier transforms, digital filters, image processing and speech recognition. Digital signal processor applications are typically characterized by real-time operation, high interrupt rates and intensive numeric computations. In addition, digital signal processor applications tend to be intensive in memory access operations and to require the input and output of large quantities of data. Digital signal processor architectures are typically optimized for performing such computations efficiently.
Microcontrollers, by contrast, involve the handling of data but typically do not require extensive computation. Microcontroller application programs tend to be longer than DSP programs. In order to limit the memory requirements of microcontroller application programs, it is desirable to provide a high degree of code density in such programs. Thus, architectures that are optimized for DSP computations typically do not operate efficiently as microcontrollers. Also, microcontrollers typically do not perform well as digital signal processors. Nonetheless, a particular application may require both digital signal processor and microcontroller functionality.
Digital signal processor designs may be optimized with respect to different operating parameters, such as computation speed and power consumption, depending on intended applications. Furthermore, digital signal processors may be designed for 16-bit words, 32-bit words, or other word sizes. A 32-bit architecture that achieves very high operating speed is disclosed in U.S. Pat. No. 5,954,811 issued Sep. 21, 1999 to Garde.
Digital signal processors frequently utilize architectures wherein two or more data words are stored in each row of memory, and two or more data words are provided in parallel to the computation unit. Such architectures provide enhanced performance, because several instructions and/or operands may be accessed simultaneously.
Notwithstanding the performance levels of current digital signal processors, there is a need for further enhancements in digital signal processor performance.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a computation unit is provided. The computation unit is preferably configured for performing digital signal processor computations. The computation unit comprises an execution unit for performing an operation on a first operand and a second operand in response to an instruction, a register file for storing operands, first and second operand buses coupled to the register file, and first and second data selectors. The first and second operand buses each carry a high operand and a low operand. The first data selector supplies the high operand or the low operand from the first operand bus to the execution unit in response to a first operand select value contained in the instruction. The second data selector supplies the high operand or the low operand from the second operand bus to the execution unit in response to a second operand select value contained in the instruction.
The execution unit may comprise an arithmetic logic unit, a multiplier and an accumulator. In one embodiment, the register file comprises first and second register banks, each having two read ports and two write ports. In another embodiment, the register file comprises a single register bank having four read ports and four write ports.
According to another aspect of the invention, a computation unit is provided. The computation unit comprises an execution unit for performing an operation on first and second operands in response to an instruction, a register file for storing operands, an operand bus coupled to the register file, the operand bus carrying a high operand and a low operand, and a data selector, responsive to an operand select value contained in the instruction, for supplying the high operand or the low operand from the operand bus to the execution unit.
According to another aspect of the invention, a method is provided for performing a digital computation. The method comprises the steps of storing operands for the computation in a register file, supplying operands from the register file on first and second operand buses, each carrying a high operand and a low operand, selecting the high operand or the low operand from the first operand bus in response to a first operand select value contained in an instruction and supplying a selected first operand to the execution unit, selecting the high operand or the low operand from the second operand bus in response to a second operand select value contained in the instruction and supplying a selected second operand to the execution unit, and performing an operation specified by the instruction on the operands selected from the first and second operand buses.
According to another aspect of the invention, a digital signal processor computation unit is provided. The digital signal processor computation unit comprises first and second execution units for performing operations in response to an instruction and for producing first and second results, a result register for storing the results of the operations, the result register having first and second locations, and result swapping logic, coupled between the first and second execution units and the result register, for swapping the first and second results between the first and second locations in the result register in response to result swapping information contained in the instruction.
The first and second execution units may comprise first and second arithmetic logic units for performing add and subtract operations. The first and second execution units are separately controllable and may perform the same or different operations in response to operation code information contained in the instruction. The first and second arithmetic logic units may comprise 16-bit arithmetic logic units which are configurable as a 32-bit arithmetic logic unit. The first and second locations in the result register may comprise high and low halves of the result register. The result register may comprise a register in a register file.
According to another aspect of the invention, a method is provided for performing digital signal computations. The method comprises the steps of performing operations in first and second execution units in response to an instruction and producing first and second results, storing the results of the operations in a result register having first and second locations, and swapping the first and second results with respect to the first and second locations in the result register, in response to result swapping control information contained in the instruction.
According to another aspect of the invention, a digital signal processor computation unit is provided. The digital signal processor computation unit comprises first and second execution units for performing operations in response to an instruction and for producing first and second results, a result register for storing the results of the operations, the result register having first and second locations, and means for swapping the first and second results with respect to the first and second locations in the result register, in response to result swapping control information contained in the instruction.
According to another aspect of the invention, a digital signal processor computation core is provided. The digital signal processor computation core comprises first and second execution units for performing first and second operations in response to control signals, and control logic for providing the control signals to the first and second execution units in response to control information con
Edmondson John
Fridman Jose
Hoffman Marc
Analog Devices Inc.
Kim Kenneth S.
Wolf Greenfield & Sacks P.C.
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