Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
2011-04-12
2011-04-12
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S043000, C712S229000, C711S125000, C711S129000
Reexamination Certificate
active
07925866
ABSTRACT:
A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions. The processing circuitry is then arranged only to execute an instruction in the sequence using the corresponding pre-decoded instruction from the cache if a current processor state of the processing circuitry matches the indication of the speculative processor state stored in the cache for that instruction. This provides a simple and effective mechanism for detecting instructions that have been corrupted by the pre-decoding operation due to an incorrect assumption of processor state.
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Craske Simon John
Greenhalgh Peter Richard
Rose Andrew Christopher
Zardini Max
ARM Limited
Nixon & Vanderhye P.C.
Treat William M
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