Secondary trace build from a cache of translations in a...

Secure execution of program instructions provided by network...

Selection of decoder output from two different length...

Selective zero extension based on operand size

Shift prefix instruction decoder for modifying register...

Shift prefix instruction decoder for modifying register...

Side tables annotating an instruction stream

Signal processor executing compressed instructions that are deco

Single shared instruction predecoder for supporting multiple...

Specialized millicode instruction for editing functions

Specialized millicode instruction for translate and test

Static instruction decoder utilizing a circular queue to decode

Status register update logic optimization

Storing stack operands in registers

Structure for a single shared instruction predecoder for...

Superscalar instruction decoder including an instruction queue

Symmetrical multiprocessing bus and chipset used for...

System and method for expanding the instruction set of an...

System and method for extracting instruction boundaries in a...

System and method for generating responses for inputs using a hy