Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1995-06-07
2003-05-13
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
Reexamination Certificate
active
06564314
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to compressed instructions for a computer system and methods of using a computer system with compressed instructions.
BACKGROUND OF THE INVENTION
The manner in which computer instructions are encoded is important as it will affect the bit length of instructions, and thereby code density, as well as the speed of decoding the instructions during an execution sequence for the instructions. It also affects the memory access time needed to fetch the instructions.
Common operations by a processor in a computer system require identification of one or more sources of data to form an input to the processor as well as a destination for receiving the result of operating the processor. Conventional reduced instruction set computers (RISC devices) have used instructions all of a common bit length and format defining both the operation to be carried out by the processor as well as identification of two sources of data for use in the operation as well as a destination for the result of the operation. Such instructions have been used to manipulate data that is found in addressable store locations such as registers or memory. Such instructions of the same size usually have little variation in format and consequently simplify the decoding operation. However when using a processor in a pipelined operation to execute a sequence of instructions it may be necessary to hold a plurality of live data items which are accessible by subsequent instructions and this requires sufficient number of addressable locations to be identified by an instruction that it imposes a limit on the shortness of the instructions that can be used. Furthermore, a number of instructions may not necessarily require the full range of register addresses that can be handled by a single instruction and consequently the fixed length instructions may unnecessarily increase the bit length of an instruction. This means that the memory capacity needed to hold an instruction sequence as well as the memory accessing time needed to obtain a sequence of instructions can be unnecessarily increased.
Other systems are known with complex instructions, (CISC devices). Long instructions have provided the facility for identifying the addresses of more data stores used for holding live data during the pipelined processing of an instruction sequence. However such long instructions have required greater access time in obtaining the instructions from memory and may involve more extensive decoding needing more cycles of operation to achieve decoding of each instruction.
It is an object of the present invention to provide a computer system with compact instructions avoiding the need for redundant bit locations and allowing simple decoding of instructions.
It is a further object of the invention to provide a computer system having variable length instructions some of which are compressed to avoid redundant bit locations.
It is a further object of the invention to provide a system for expanding compressed instructions for use by a processor in a computer system.
SUMMARY OF THE INVENTION
The invention provides a computer system having logic circuitry arranged to respond to an instruction set comprising a plurality of selectable instructions of different bit length, each instruction being based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length, wherein some instructions omit a selected one of said fields and include an identifier of less bit length than the omitted field to indicate which field is omitted, thereby compressing the bit length of the instruction.
Preferably each instruction includes control bits in addition to said instruction fields.
Preferably said control bits provide an indication of the length of the instruction and identify which fields are present or omitted from the instruction.
Said control bits may provide an indication of the designation of data in one or more of said fields.
Preferably said selected one of said fields which is omitted is an identifier for a data holding location. Said data holding location may be a register.
In some embodiments said selected one of said fields which is omitted is an identifier of a first in first out data store arranged to hold simultaneously a plurality of data values. In this way a single address in an instruction may indicate a storage location for holding a plurality of live data values.
Preferably the omission of any selected field designates an implicit storage location not requiring address data in the instruction, and said logic circuitry is arranged to access said implicit storage location in response to the omission of the or each omitted field. Preferably said implicit storage location comprises a first in first out data store arranged to hold simultaneously a plurality of data values. In this way a plurality of live data values may be held during the operation of the sequence of instructions without increasing the number of address bits provided in each instruction.
Commonly said instruction fields in said format of predetermined bit length provide indications of two data source locations and a data destination location thereby indicating the source of data for use in execution of the instruction and the destination of a result of execution of the instruction.
Each instruction may have a bit length equal to an integral number of bytes and each field may have a bit length less than one byte.
The present invention also provides a method of compressing instruction bit length in a computer system which method comprises storing in a data store a plurality of instructions of variable length, each instruction being based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length, wherein some instructions are formed with omission of at least one selected said field and indicate which field or fields are omitted by an identifier of less bit length than the omission, thereby compressing the bit length of the instruction.
The present invention also provides a method of generating instructions for use in a computer system arranged to execute instructions selected from an instruction set comprising a plurality of instructions each based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length, which method comprises inputting instructions wherein at least some are compressed by omission of at least one field and include an identifier of less bit length than the omitted field to indicate which field is omitted, decoding said identifier and expanding the bit length of the instruction to restore the omitted field, and outputting the expanded instructions.
The invention also provides a method of operating a computer system comprising executing a plurality of instructions selected from an instruction set comprising a plurality of selectable instructions of different bit length, each instruction being based on a format of predetermined bit length and a predetermined sequence of instruction fields each of a respective predetermined bit length, wherein some instructions omit at least one selected said field and include an identifier of less bit length than the omitted field to indicate which field is omitted, thereby compressing the bit length of the instruction.
An embodiment of the present invention will now be described by way of example and with reference to the accompanying drawings.
REFERENCES:
patent: 3275989 (1966-09-01), Glaser et al.
patent: 3626374 (1971-12-01), Chinlund
patent: 4241397 (1980-12-01), Strecker
patent: 5249273 (1993-09-01), Yoshitake et al.
patent: 5420923 (1995-05-01), Beyers et al.
patent: 5434568 (1995-07-01), Moll
patent: 5440701 (1995-08-01), Matsuzaki et al.
patent: 5463746 (1995-10-01), Brodnax et al.
patent: 0 073 424 (1983-03-01), None
patent: A-2 073 424 (1983-03-01), None
patent: A-0 380 849 (1990-08-01), None
Motorola, MC68030 User's Manual, Prentice-Hall, 1989, p. 3-35.*
The
May Michael David
Sidwell Nathan Mackenzie
Sturges Andrew Craig
Eng David Y.
Morris James H.
SGS-Thomson Microelectronics Limited
Skrivanek, Jr. Robert A.
Wolf Greenfield & Sacks P.C.
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