Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
Reexamination Certificate
1998-09-21
2001-08-14
An, Meng-Al T. (Department: 2154)
Electrical computers and digital processing systems: processing
Instruction decoding
Predecoding of instruction component
C712S024000
Reexamination Certificate
active
06275927
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessors and, more particularly, to decoding variable length instructions within a microprocessor.
2. Description of the Relevant Art
The number of software applications written for the x86 instruction set is quite large. As a result, despite the introduction of newer and more advanced instruction sets, microprocessor designers have continued to design microprocessors capable of executing the x86 instruction set.
The x86 instruction set is relatively complex and is characterized by a plurality of variable-length instructions. A generic format illustrative of the x86 instruction set is shown in FIG.
1
. As illustrated in the figure, an x86 instruction consists of from one to five optional prefix bytes
102
, followed by an operation code (opcode) field
104
, an optional addressing mode (Mod R/M) byte
106
, an optional scale-index-base (SIB) byte
108
, an optional displacement field
110
, and an optional immediate data field
112
.
The opcode field
104
defines the basic operation for a particular instruction. The default operation of a particular opcode may be modified by one or more prefix bytes
102
. For example, one of prefix bytes
102
may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times. The opcode field
104
follows prefix bytes
102
, if present, and may be one or two bytes in length. The addressing mode (Mod R/M) byte
106
specifies the registers used as well as memory addressing modes. The scale-index-base (SIB) byte
108
is used only in 32-bit base-relative addressing using scale and index factors. A base field within SIB byte
108
specifies which register contains the base value for the address calculation, and an index field within SIB byte
108
specifies which register contains the index value. A scale field within SIB byte
108
specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value. The next instruction field is a displacement field
110
, which is optional and may be from one to four bytes in length. Displacement field
110
contains a constant used in address calculations. The optional immediate field
112
, which may also be from one to four bytes in length, contains a constant used as an instruction operand. The shortest x86 instructions are only one byte long, and comprise a single opcode byte. The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes.
The complexity of the x86 instruction set poses many difficulties in implementing high performance x86-compatible microprocessors. In particular, the variable length of x86 instructions makes decoding instructions difficult. Decoding instructions typically involves determining the boundaries of an instruction and then identifying each field within the instruction, e.g., the opcode and operand fields. Decoding typically takes place once the instruction is fetched from the instruction cache before execution.
One method for determining the boundaries of instructions involves generating a number of predecode bits for each instruction byte read from main memory. The predecode bits provide information about the instruction byte they are associated with. For example, an asserted predecode start bit indicates that the associated instruction byte is the first byte of an instruction. Similarly, an asserted predecode end bit indicates that the associated instruction byte is the last byte of an instruction. Once the predecode bits for a particular instruction byte are calculated, they are stored together with the instruction byte in an instruction cache. When a “fetch” is performed, i.e., a number of instruction bytes are read from the instruction cache, the associated start and end bits are also read. The start and end bits may then be used to generate valid masks for the individual instructions with the fetch. A valid mask is a series of bits in which each bit corresponds to a particular instruction byte. Valid mask bits associated with the first byte of an instruction, the last byte of the instruction, and all bytes in between the first and last bytes of the instruction are asserted. All other valid mask bits are not asserted. Turning now to
FIG. 2
, an exemplary valid mask is shown. The figure illustrates a portion of a fetch
120
and its associated start and end bits
122
and
124
. Assuming a valid mask
126
for instruction B
128
is to be generated, start and end bits
122
and
124
would be used to generate the mask. Valid mask
126
could then be used to mask off all bytes within fetch
120
that are not part of instruction B
128
.
Once the boundaries of an instruction have been determined, the fields within the instruction, e.g., the opcode and operand fields, may be identified. Once again, the variable length of x86 instructions complicates the identification process. In particular, the optional prefix bytes within an x86 instruction create further complications. For example, in some instructions the opcode will begin with the first byte of the instruction, while others may begin with the second, third, or fourth byte.
To perform the difficult task of decoding x86 instructions, a number of cascaded levels of logic are typically used. Thus, decoding may require a number of clock cycles and may create a significant delay before any instructions are available to the functional stages of the microprocessor's pipeline. As microprocessors increase the number of instructions they are able to execute per clock cycle, instruction decoding may become a performance limiting factor. Therefore, a mechanism for simplifying the complexity and time required for instruction decoding is needed.
SUMMARY
The problems outlined above are reduced in large part by a microprocessor capable of predecoding variable-length instructions in a manner that reduces length variations in the instructions set. By compressing each instruction's prefix bytes into a single compressed prefix byte, potential variation in instruction length is reduced. Advantageously, this may serve to decrease the time needed for decoding instructions.
In one embodiment, a microprocessor configured to compress prefix bytes may comprise a predecode unit and an instruction cache. The predecode unit may be configured to receive variable length instructions from a memory subsystem. A subset of the instructions may have no prefix bytes, while others may have one or more prefix bytes. The predecode unit is configured to detect the prefix bytes associated with each instruction and compress them into a single compressed prefix byte. The predecode unit may also perform other decoding functions and or instruction padding. The instruction cache is coupled to the predecode unit and is configured to receive and store the partially decoded instructions and their associated compressed prefix bytes. The instruction cache is configured to output the instructions and their compressed prefix bytes in response to receiving corresponding fetch addresses. A computer system employing one or more microprocessors as described above in conjunction with other peripheral devices (e.g., a communications modem) is also contemplated.
A method for executing variable length instructions is also contemplated. In one embodiment, the method comprises reading a plurality of instruction bytes from a memory subsystem, and then predecoding the instruction bytes. Predecoding involves detecting starting, ending, and prefix bytes for each instruction. The prefix bytes are compressed into a single compressed prefix byte; and then stored with the instructions in an instruction cache. In one embodiment, the prefix bytes are compressed by encoding operand size prefix bytes address size prefix bytes into a single operand size bit, address size prefix bytes into a single address size bit, a
Advanced Micro Devices.
An Meng-Al T.
Chang Jung-won
Christen Dan R.
Conley Rose & Tayon PC
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