Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
1998-06-12
2001-04-17
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S024000
Reexamination Certificate
active
06219779
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to microprocessors and is a technique for making effective use of redundant areas and unused areas that are present within instructions.
2. Description of the Prior Art
In recent years, increases in processing capability and processing speed of appliances using embedded microprocessors have led to an increasing demand for microprocessors (hereinafter simply referred to as “processors”) that can execute programs with high code efficiency. This means that it is preferable for there to be no redundant areas or unused areas in the instructions which compose a program.
In particular, when using fixed length instructions, such as VLIW (Very Long Instruction Words), there are cases when it is necessary to insert redundant codes, such as no-operation codes (“nop” codes), into instructions. VLIW are composed of a plurality of operation fields, with each operation field specifying an operation which corresponds to one of a plurality of operation units provided within a processor. Due to interdependencies between operations, however, it is not always possible to process a plurality of operations using parallel processing.
One conventional method of avoiding the decreases in code efficiency that accompany the insertion of “nop” codes is the VLIW-type computer system disclosed by Japanese Laid-Open Patent Application H08-161169.
FIG. 1
shows the instruction format used in the above technique.
As shown in
FIG. 1
, when a “nop” code needs to be inserted into operation field#2, this technique inserts a constant that is to be used by a different operation in place of the “nop” code into operation field #2 and inserts instruction validation information into one part of operation field #1 to show that the constant has been inserted. When executing this instruction, a processor first refers to the instruction validation information and so determines that only a constant is present in operation field #2. The processor then uses this constant as the operand of an operation. In this way, the existence of redundant areas within instructions due to the insertion of “nop” codes can be avoided.
The above technique, however, has a drawback in that the size of the constants that can be inserted into the redundant areas is limited.
As one example, when it is necessary to insert a “nop” code into a 32-bit operation field, it is not possible to insert any part of a 64-bit constant. Similarly, when there is an unused 8-bit area in a fixed 32-bit instruction, it is only possible to use the unused area when inserting a constant which is 8 bits long or shorter. In this case, it is not possible to insert an absolute address which is expressed using 32 bits.
While the above technique may be effective when there is a relatively large redundant area in an instruction, when instructions have a relatively short length, such as 32 bits, any redundant area in the instructions will naturally be short, preventing the insertion of constants into a large number of redundant areas when using the above technique. This constitutes a major problem.
As a potential solution to the above problem, a processor could conceivably be provided with a specialized register (“constant register”) for storing constants. However, a processor provided with such a register would suffer from increases in processing time for context switching during multitasking. To perform multiple tasks by switching the processing according to time division, the processor needs to operate as follows. The processor needs to switch to the operating system during the execution of a task, to save the information (“context”) that is required for the recommencement of the execution of the task into a saving area, such as memory, and then to restore the context of the next task to be executed. This procedure is called “context switching”, and has to be performed with a high frequency. When a value stored in a constant register is also included in a context, this adds to the processing time required when performing task switching.
SUMMARY OF THE INVENTION
In view of the stated problems, it is a first object of the present invention to provide a processor for which the size of constants that may be inserted into redundant areas in instructions is not restricted by the word length of the instructions. By doing so, it is possible to avoid the presence of even small redundant areas in instructions. This supports the generation of programs with high code efficiency.
A second object of the present invention is to provide a processor that achieves the first object of the present invention and can also reduce the processing time required for context switching.
The first object of the present invention can be achieved by a processor for decoding and executing an instruction, the processor including: an instruction register for storing the instruction; a decoding unit for decoding the stored instruction; a constant register including a storage region for storing a constant; a constant storing unit which, when the decoding unit has decoded that the instruction includes a constant that should be stored into the constant register, stores the constant included in the instruction into the constant register if no valid constant is stored in the constant register, and, if a valid constant is already stored in the constant register, stores the constant included in the instruction into the constant register so as to retain the valid constant; and an execution unit which, when the decoding unit has decoded that the instruction specifies an operation which uses the constant register, reads an entire value stored in the constant register and executes the operation in the constant register.
With the stated construction, pieces of a constant that are provided in a plurality of instructions can be accumulated (in a digit direction) in the constant register to restore the original constant. Accordingly, even when there is a small redundant area in an instruction, this small area can be used to store one piece of a constant whose word length exceeds that of the small area. This assists in the generation of programs with high code efficiency.
Here, the constant storing unit may store the constant included in the instruction into the constant register after shifting the valid constant that is already stored in the constant register, the valid constant and the constant included in the instruction being linked in a digit direction in the constant register.
With the stated construction, a constant can be accumulated by merely storing each piece of the constant in the same position in the constant register, so that there is no need to consider which position in the constant register should be used next.
Here, the constant storing unit may shift the valid constant to a higher bit position in the constant register and store the constant included in the instruction by inserting the constant at a lower bit position.
With the stated construction, constants are inserted into the constant register so as to be aligned with the least significant bit. As a result, a processor which is especially well suited to the setting of variable-length constants in the constant register can be achieved.
Here, the processor may further include an extension unit for performing extension processing to add at least one of a sign extension and a zero extension to the constant.
With the stated construction, when the constant stored in the constant register is used as an operand, it can be guaranteed that the operand will have been given a suitable zero extension or sign extension.
Here, the extension unit may perform the extension processing on the constant included in the instruction before the constant is stored into the constant register.
With the stated construction, it can be guaranteed that a constant stored in the constant register will have been given an extension, and since it becomes no longer necessary to give a constant read from the constant register an extension, the time taken by operations that use the constant
Heishi Taketo
Higaki Nobuo
Suzuki Masato
Takayama Shuichi
Tanaka Tetsuya
Follansbee John A.
Matsushita Electric - Industrial Co., Ltd.
Price and Gess
LandOfFree
Constant reconstructing processor which supports reductions... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Constant reconstructing processor which supports reductions..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Constant reconstructing processor which supports reductions... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2513310