Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2005-06-14
2005-06-14
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
Reexamination Certificate
active
06907515
ABSTRACT:
A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data310, 312, 314, 316which may or may not be valid. Programs that use the second execution mechanism are responsible for the writing of its own configuration data with this being indicated as being necessary by a configuration valid indicator CV set to indicate that the configuration is invalid by the operating system300upon detecting an appropriate process switch.
REFERENCES:
patent: 3889243 (1975-06-01), Drimak
patent: 4236204 (1980-11-01), Groves
patent: 4587632 (1986-05-01), Ditzel
patent: 4779188 (1988-10-01), Gum et al.
patent: 4888771 (1989-12-01), Benignus et al.
patent: 4922414 (1990-05-01), Holloway
patent: 4969091 (1990-11-01), Muller
patent: 5101346 (1992-03-01), Ohtsuki
patent: 5136696 (1992-08-01), Beckwith
patent: 5455775 (1995-10-01), Huber
patent: 5619665 (1997-04-01), Emma
patent: 5638525 (1997-06-01), Hammond
patent: 5659703 (1997-08-01), Moore
patent: 5740461 (1998-04-01), Jaggar
patent: 5742802 (1998-04-01), Harter
patent: 5752035 (1998-05-01), Trimberger
patent: 5784584 (1998-07-01), Moore
patent: 5809336 (1998-09-01), Moore
patent: 5813039 (1998-09-01), Wakui
patent: 5838948 (1998-11-01), Bunza
patent: 5875336 (1999-02-01), Dickol
patent: 5892966 (1999-04-01), Petrick
patent: 5924127 (1999-07-01), Kawamoto et al.
patent: 5925123 (1999-07-01), Tremblay
patent: 5926832 (1999-07-01), Wing
patent: 5937193 (1999-08-01), Evoy
patent: 5953741 (1999-09-01), Evoy
patent: 6003126 (1999-12-01), Huynh
patent: 6009499 (1999-12-01), Koppala
patent: 6009509 (1999-12-01), Leung
patent: 6014723 (2000-01-01), Tremblay
patent: 6021469 (2000-02-01), Tremblay
patent: 6026485 (2000-02-01), O'Connor
patent: 6031992 (2000-02-01), Cmelik
patent: 6038643 (2000-03-01), Tremblay
patent: 6070173 (2000-05-01), Huber
patent: 6088786 (2000-07-01), Feierbach
patent: 6122638 (2000-09-01), Huber
patent: 6125439 (2000-09-01), Tremblay
patent: 6148391 (2000-11-01), Petrick
patent: 6298434 (2001-10-01), Lindwer
patent: 6317872 (2001-11-01), Gee
patent: 6338134 (2002-01-01), Leung
patent: 6349377 (2002-02-01), Lindwer
patent: 6374286 (2002-04-01), Gee
patent: 6442753 (2002-08-01), Gerard et al.
patent: 6606743 (2003-08-01), Raz
patent: 2 307 072 (1997-05-01), None
patent: 2 365 584 (2002-02-01), None
patent: 00/39670 (2000-07-01), None
Y. Patt,Introduction to Computer Systems From Bits and Gates to C and Beyond, 1999, pp. 1-517.
M. Ertl, “Stack Caching for Interpreters” 1994, pp. 1-13.
M. Ertl, “Stack Caching for Interpreters” 1995, pp. 1-13.
M. Ertl, “Implementation of Stack-Based Languages on Register Machines” Apr. 1996, pp. 1-4.
J. O'Connor et al, “PicoJava-I: The Java Virtual Machine in Hardware”IEEE MicroA Case for Intelligent RAM, Mar./Apr. 1997, pp. 45-53.
K. Andrews et al, “Migrating a CISC Computer Family Onto RISC Via Object Code Translation” 1992, pp. 213-222.
“PicoJava I Microprocessor Core Architecture” Oct. 1996, pp. 1-8, Sun Microsystems.
M. Ertl, “A New Approach to Forth Native Code Generation” 1992.
M. Maierhofer et al, “Optimizing Stack Code” 1997, p. 19.
D. Ungar et al, “Architecture of SOAR: Smalltalk on a RISC” The 11thAnnual International Symposium on Computer Architecture, Jun. 1984, pp. 188-197.
O. Steinbusch, “Designing Hardware to Interpret Virtual Machine Instructions” Feb. 1998, pp. 1-59.
R. Kapoor et al, “Stack Renaming of the Java Virtual Machine” Dec. 1996, pp. 1-17.
A. Yonezawa et al, “Implementing Concurrent Object-Oriented Languages in Multicomputers”Parallel Distributed Technology(Systems and Applications) May 1993, pp. 49-61.
C. Hsieh et al, “Java Bytecode to Native Code Translation; The Caffeine Prototype and Preliminary Results” IEEE/ACM International Symposium on Microarchitecture, Dec. 1996, pp. 90-97.
Y. Patt et al,Introduction to Computer Systems From Bits and Gates to C and Beyond, 2001, pp. 1-526.
Sun Microsystems PicoJava Processor Core Data Sheet, Dec. 1997, pp. 1-6.
H. McGhan et al, PicoJava A Direct Execution Engine for Java Bytecode, Oct. 1998, pp. 22-26.
C. Glossner et al, “Parallel Processing” Euro-Par 1997: Passau, Germany, Aug. 1997.
Y. Patt,Introduction to Computer Systems From Bits and Gates to C and Beyond, 1999, pp. 10-12 & 79-82.
Espresso—The High Performance Java Core Specification, Oct. 2001, pp. 1-33, Aurora VLSI, Inc.
J. Gosling, “Java Intermediate Bytecodes” 1995, pp. 111-118.
P. Koopman, Jr. “Stack Computers The New Wave” 1989, pp. 1-234.
M. Mrva et al., “A Scalable Architecture for Multi-Threaded JAVA Applications” Design Automation and Test in Europe, Feb. 1998, pp. 868-874.
L. Chang et al, “Stack Operations Folding in Java Processors”IEEE Proc.—Comput. Digit. Tech., vol. 145, No. 5, pp. 333-340 Sep. 1998.
L. Ton et al, Proceedings of the '97 International Conference on Parallel and Distributed Systems, “Instruction Folding in Java Processor”, pp. 138-143, Dec. 1997.
K. Buchenrieder et al, “Scalable Processor Architecture for Java With Explicit Thread Support”Electronics Lettersvol. 33, No. 18, pp. 1532+, Aug. 1997.
C. Chung et al, Proceedings of the '98 International Conference on Parallel and Distributed Systems, “A Dual Threaded Java Processor for Java Multithreading” pp. 693-700, Dec. 1998.
I. Kazi et al, “Techniques for Obtaining High Performance in Java Programs” Sep. 2000, pp. 213-240.
R. Kieburtz, “A RISC Architecture for Symbolic Computation” 1987, pp. 146-155.
M. Berekovic et al, “Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications”Signal Processing Systems SIPS 98, pp. 479-488, 1997.
P. Deutsch, “Efficient Implementation of the Smalltalk-80 System” 1983, pp. 297-302.
“Rockwell Produces Java Chip” Sep. 1997, CNET News.com.
Y. Patt et al,Introduction to Computing Systems from Bits and Gates to C and Beyond, 2001, pp. 1-16, 91-118 & 195-209.
Dornan Christopher Bentley
Seal David James
Arm Limited
Coleman Eric
Nixon & Vanderhye P.C.
LandOfFree
Configuration control within data processing systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Configuration control within data processing systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Configuration control within data processing systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3494736