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Reconfigurable CPU with second FSM control unit executing...

Electrical computers and digital processing systems: processing – Instruction decoding
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Reducing the length of lower level instructions by splitting...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Register file access

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Register move instruction for section select of source operand

Electrical computers and digital processing systems: processing – Instruction decoding
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Register move instruction for section select of source operand

Electrical computers and digital processing systems: processing – Instruction decoding
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Register set extension for compressed instruction set

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Removing local RAM size limitations when executing software...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
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Replacing displacement in control transfer instruction with enco

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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