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Parallel pack instruction method and apparatus

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Parallel subword instructions with distributed results

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Parsing-enhancement facility using a translate-and-test...

Electrical computers and digital processing systems: processing – Instruction decoding
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Patchable and/or programmable decode using predecode selection

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Patchable and/or programmable decode using predecode selection

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Pipeline elements which verify predecode information

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Pipeline processing machine with interactive stages operable...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Pipelined completion for asynchronous communication

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
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Pre-decode checking for pre-decoded instructions that cross...

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Pre-decoding variable length instructions

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Predecoding technique for indicating locations of opcode bytes i

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Predicting a sequence of variable instruction lengths from previ

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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Process for translating instructions for an arm-type...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Processing apparatus for storing branch history information...

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Processing instruction without operand by inferring related...

Electrical computers and digital processing systems: processing – Instruction decoding
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Processing of binary data for compression

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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Processor

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
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Processor adapted to receive different instruction sets

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Processor adapted to receive different instruction sets

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Processor and method of automatic instruction mode switching...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
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