Way prediction unit and a method for operating the same

Details Way prediction unit and a method for operating the same Way prediction unit and a method for operating the same

1997-04-09

1998-12-08

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

364DIG1, 364DIG2, 3642434, 36424341, 3642318, 395376, 39580001, 711118, 711125, 711140, 711144, 711145, G06F 1200, G06F 1300

Patent

active

058484337

ABSTRACT:
A way prediction unit for a superscalar microprocessor is provided which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The way prediction unit is intended for high frequency microprocessors in which associative caches tend to be clock cycle limiting, causing the instruction fetch mechanism to require more than one clock cycle between fetch requests. Therefore, an instruction fetch can be made every clock cycle using the predicted fetch address until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.

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