Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1999-11-09
2000-09-05
Thai, Tuan V.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711137, 712239, G06F 1200, G06F 1300
Patent
active
061157929
ABSTRACT:
A set-associative cache memory configured to use multiple portions of a requested address in parallel to quickly access data from a data array based upon stored way predictions. The cache memory comprises a plurality of memory locations, a plurality of storage locations configured to store way predictions, a decoder, a plurality of pass transistors, and a sense amp unit. A subset of the storage locations are selected according to a first portion of a requested address. The decoder is configured to receive and decode a second portion of the requested address. The decoded portion of the address is used to select a particular subset of the data array based upon the way predictions stored within the selected subset of storage locations. The pass transistors are configured select a second subset of the data array according to a third portion of the requested address. The sense amp unit then reads a cache line from the intersection of the first subset and second subset within the data array.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4764861 (1988-08-01), Shibuya
patent: 4807115 (1989-02-01), Torng
patent: 4853840 (1989-08-01), Shibuya
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 4943908 (1990-07-01), Emma et al.
patent: 4984154 (1991-01-01), Hanatani et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5142634 (1992-08-01), Fite et al.
patent: 5185868 (1993-02-01), Tran
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5230068 (1993-07-01), Van Dyke et al.
patent: 5235697 (1993-08-01), Steely, Jr. et al.
patent: 5283873 (1994-02-01), Steely, Jr. et al.
patent: 5327547 (1994-07-01), Stiles et al.
patent: 5345587 (1994-09-01), Tran
patent: 5381533 (1995-01-01), Peleg et al.
patent: 5418922 (1995-05-01), Liu
patent: 5423011 (1995-06-01), Blaner et al.
patent: 5454117 (1995-09-01), Puziol et al.
patent: 5485587 (1996-01-01), Matsuo et al.
patent: 5521306 (1996-05-01), Tran
patent: 5619676 (1997-04-01), Fukuda et al.
patent: 5640532 (1997-06-01), Thome et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5701435 (1997-12-01), Chi
patent: 5752069 (1998-05-01), Roberts et al.
patent: 5764946 (1998-06-01), Tran
patent: 5835951 (1998-11-01), McMahan
XP 000525181 Calder, et al, "Next Cache Line and Set Prediction," Department of Computer Science, University of Colorado, 8345 Computer Architecture News, May 23, 1995, No. 2, pp. 287-296.
XP 000397920 Uchiyama, et al, "The Gmicro/500 Superscalar Microprocessor with Branch Buffers," 8207 IEEE Micro, Oct. 13, 1993, No. 5, pp. 12-22.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4, 1994.
Slater, M., "AMD's Microprocessor K5 designed to Outrun Pentium" (Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Rupley, et al, "P6: The Next Step?" PC Magazine, Sep. 12, 1995, 16 pages.
Halfhill, "AMD K6 Takes on Intel P6," BYTE Magazine, Jan. 1996, 4 pages.
Patterson, et al, "Computer Architecture: A Quantitative Approach," Section 8.3, pp. 408-425, published by Morgan Kaufmann Publishers, Inc., 1990.
"Intel Architecture Software Developer's Manual, vol. 1: Basic Architecture", Intel Corporation, Prospect IL, 1996, 1997, Chapter 8: Programming With The Intel MMX.TM. Technology, pp 8-1 through 8-15.
Holstad, S., "Tutorial Tuesday: Decoding MMX" Jan. 14, 1997, Earthlink Network, Inc. copyright 1997, 5 pages (see http://www.earthlink.net/daily/Tuesday/MMX).
"Intel MMX.TM. Technology--Frequently Asked Questions" 6 pages (see http://www.intel.com/drg/mmx/support/faq/htm).
Advanced Micro Devices , Inc.
Merkel Lawrence J.
Thai Tuan V.
LandOfFree
Way prediction logic for cache array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Way prediction logic for cache array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Way prediction logic for cache array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2223433