Random access memory controller with out of order execution
Random access memory controller with out of order execution
Read data valid loop-back for high speed synchronized DRAM...
Read priority caching system and method
Read/write timing for maximum utilization of bi-directional...
Read/write timing for maximum utilization of bidirectional read/
Reading a FIFO in dual clock domains
Reading extended data burst from memory
Receiver for a memory controller and method thereof
Reconfigurable data cache controller
Redundant dual bank architecture for a simultaneous...
Redundant processor controlled system
Register bank
Remote data copy using a prospective suspend command
Robust interface for high speed memory access
ROM addressing method for an ADPCM decoder implementation
Rule-based optimizing DRAM controller