Read/write timing for maximum utilization of bidirectional read/

Details Read/write timing for maximum utilization of bidirectional read/ Read/write timing for maximum utilization of bidirectional read/

1997-09-19

2000-07-11

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711163, 711168, 711169, 365194, 36523003, G06F 1200

Patent

active

060887745

ABSTRACT:
A method and apparatus for optimizing the efficiency of a data bus for a memory device. Extra latency is added between the time a memory controller issues a write instruction and the time the data is transferred on the data bus. This additional latency is optimized to reduce the number of idle time slots on the data bus when switching between a read instruction and a write instruction. Programmable registers are provided for adjusting the amount of latency.

REFERENCES:
patent: 4866675 (1989-09-01), Kawashima
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5490082 (1996-02-01), Rowson
patent: 5784582 (1998-07-01), Hughes
patent: 5802586 (1998-09-01), Jones et al.
patent: 5813023 (1998-09-01), McLaury
patent: 5845314 (1998-12-01), Ishida

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