Reading a FIFO in dual clock domains

Details Reading a FIFO in dual clock domains Reading a FIFO in dual clock domains

2000-03-23

2003-08-05

McLean-Mayo, Kimberly (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S154000, C711S100000, C365S233100, C365S230050

Reexamination Certificate

active

06604179

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains generally to computer circuits. In particular, it pertains to a first-in first-out buffer whose output can be read by different circuits at different times using different clocks.
2. Description of the Related Art
Modem computer systems frequently have to move data between two environments using different clocks, the clocks being unrelated in speed, phase, or both. Examples would be moving data between a disk and main memory, between a memory and a processor, or between a fast bus and a slow bus. To avoid having the faster device wait on the slower device to complete the transfer, the data transfer is typically implemented by using an intervening buffer, such as a first-in-first-out buffer (FIFO), to temporarily store the data as it transitions from one environment to the other. Data can be written into the buffer using the clock from the input side of the buffer, and the data can be subsequently read from the buffer using the clock on the output side of the buffer. While this approach can allow the devices on each side to operate at their own speed, the disparity between the phase and timing of the clocks can cause inefficient operation, especially when the buffer is full and the faster device must wait until the slower device removes data and makes more buffer space available.
Processor speeds have improved so rapidly that this improvement has created a problem with getting data to the processor as fast as the processor can use it. The use of graphics processing has also created a need to transfer large amounts of data from memory in a short time. Various approaches to increase data transfer rates to/from memory have been devised, such as wider data buses and burst transmissions, which transfer a burst of data from sequential locations once the initial memory address is specified, without requiring that the addresses following the initial address be specified.
In connection with burst mode transfers, the command lines and data lines are sometimes separated into two different buses, so that the next command sequence can be initiated before the current data transfer is complete. In fact, it is possible for multiple commands to be completely issued on the bus before the data starts returning from the first command. In addition, the command sequence can require that different pieces of related command data be sent out at different times. A conventional approach to resolve this issue is to place both pieces of command data in the same serial buffer, with a predetermined number of no-op commands between them to implement a delay between them. This takes up space in the buffer that could be used for actual command data, thus reducing the effective size of the buffer. An alternative conventional approach is to handle the timing functions entirely with logic external to the queue. If the timing relationships are dynamically alterable or otherwise complicated, determining and implementing the correct timing relationships can require that logic to be very complex.
Since multiple devices can potentially request a memory transfer at approximately the same time, these various requests can be scheduled and queued up so the requesting devices can be released to perform other functions while waiting for their data transfer to commence and complete. This queue creates one of the aforementioned buffers between environments with different clock speeds. The scheduling of requests also creates an unpredictable time delay between the time the requesting device makes its request and the time the requested data is presented to the requesting device.
When data is being read back after a memory read request, a read data queue can be used to buffer the incoming data as it transitions from the memory side (requested device side) time domain and the host side (requesting device side) time domain. Since the original scheduling of the request causes an unknown delay before the data is actually ready in the buffer, the requesting device will most likely be occupied with some other task when the data is ready to be transferred from the buffer to the requesting device. For efficient operation, the requesting device may therefore need some advance warning that data is available so that it can prepare its own storage circuits to receive that data. Waiting until the data appears at the output of the read data queue does not provide that warning. Alternately, trying to predict when the data will be available by catching the data before it enters the read data queue involves logic using the wrong time domain. Finally, the delay time required for the data to proceed through the read data queue can be unpredictable because the queue may simultaneously contain data for multiple devices, each with its own individual setup time and transfer characteristics.
SUMMARY OF THE INVENTION
An embodiment of the invention includes a storage array containing multiple addressable storage locations, a write pointer coupled to the storage array to point to one of the storage locations as an input address, and two read pointers coupled to the storage array to point to two storage locations as output addresses. The invention also includes a first clock coupled to the storage array to clock write data into the storage array at the input address. It further includes second and third clocks coupled to the storage array to clock read data from the storage array at the two output addresses.


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Texas Instruments, FIFO Architecture, Functions and Applications, Nov. 1999, p. 13.

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