Latency reduction using negative clock edge and read flags
Latency reduction using negative clock edge and read flags
Limit algorithm using queue depth to control application...
Line rate buffer using single ported memories for variable...
Linear combiner weight memory
Linked-list early race resolution mechanism
Load balancing of disk drives
Load balancing of disk drives
Load mechanism
Logic for providing arbitration for synchronous dual-port...
Low latency synchronous memory performance switching using...
Low power consumption semiconductor memory device capable of...