Read data valid loop-back for high speed synchronized DRAM...

Details Read data valid loop-back for high speed synchronized DRAM... Read data valid loop-back for high speed synchronized DRAM...

2000-09-29

2003-02-11

Verbrugge, Kevin (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

Reexamination Certificate

active

06519688

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to synchronized memory technologies, and particularly to memory controllers for synchronous memories.
2. Background of the Invention
As synchronized memory technology progresses, there is an increasing need for developing synchronous memory controllers that can support the high clock speeds required as the state of the art for memory devices advances. Due to the improvements in processing technologies used to fabricate memory controllers, memory controller logic can be designed to run at such high clock rates. However, since typically a memory controller is externally coupled to a synchronous memory, signals exchanged between the memory controller and the synchronous memory may be delayed due to input/output (“I/O”) pads and printed circuit board (“PCB”) traces which facilitate the coupling between the memory controller and the synchronous memory.
The problem is more serious with higher clock frequencies or lower clock cycles. For example, the internal clock cycle of a high-speed memory has gone down to about 5 nanoseconds, but the delay of a signal due to impedance associated with an I/O pad and a PCB trace can be as long as about 10 nanoseconds, which is two times the value of the clock cycle. Delays like this may cause the memory controller to be out of sync with the synchronous memory. When synchronization is lost, wrong data will be latched by the memory controller in an attempt to read from the synchronous memory.
Since the delays are caused by impedance associated with the I/O pads and PCB traces, the I/O pads and PCB traces associated with a synchronized memory system must be designed and made carefully to meet the timing requirements. However, this goal is difficult to meet consistently because the I/O pads and PCB traces transmitting the signals have impedance characteristics that vary depending on the fabrication process, the voltage of the clock signal, and the operating temperature of the memory controller. These variations introduce clock uncertainty, thus reducing the actual memory clock frequency that the memory controller can use. Clock uncertainty, in turn, makes it difficult for such memory controllers to operate consistently and/or properly at high clock rates in the real world with synchronous memory.
Therefore, there is a need for a high-speed memory controller that can operate at its highest selected internal frequency or clock frequency when coupled to a synchronous memory, and still remain relatively immune from impedance variations caused by variations in fabrication process, voltage of clock signal, and operating temperature.
SUMMARY OF THE INVENTION
The present invention provides a method and system that eliminate or significantly reduce the effect of signal delays caused by I/O pads and PCB traces during the operation of a synchronized memory controller, thus allowing the memory controller to run at the highest internal clock frequency. The present invention advantageously provides a high-speed memory controller that can operate at high clock rates and remain relatively immune from impedance variations caused by fabrication processes, voltage of the clock signal, and/or operating temperature.
In one embodiment of the present invention, a memory controller is externally coupled to a synchronous memory. The memory controller generates a master clock signal to control the operation of the memory controller and the synchronous memory. A latch clock signal is generated by routing the master clock signal off-chip and then back to the memory controller through an I/O pad, at least one PCB trace, and another I/O pad. The memory controller also generates a read valid signal. The read valid signal is then routed off-chip and back to the memory controller as a read valid loop back signal. The read valid signal is routed off-chip via an I/O pad, at least one PCB trace, and another I/O pad. The memory controller latches read data from the synchronous memory based on the latch clock signal and the read valid loop back signal.


REFERENCES:
patent: 6078514 (2000-06-01), Takemae et al.
patent: 6256235 (2001-07-01), Lee
patent: 6449727 (2002-09-01), Toda
patent: 2001/0024135 (2001-09-01), Harrison
patent: 2001/0047450 (2001-11-01), Gillingham et al.
patent: 2002/0018396 (2002-02-01), Morita et al.

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