Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-08-15
2006-08-15
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S106000, C711S158000
Reexamination Certificate
active
07093094
ABSTRACT:
A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.
REFERENCES:
patent: 5564052 (1996-10-01), Nguyen et al.
patent: 5809563 (1998-09-01), Yamada et al.
patent: 5941983 (1999-08-01), Gupta et al.
patent: 6088772 (2000-07-01), Harriman et al.
patent: 6145073 (2000-11-01), Cismas
patent: 6219747 (2001-04-01), Banks et al.
patent: 6263430 (2001-07-01), Trimberger et al.
patent: 6297832 (2001-10-01), Mizuyabu et al.
patent: 6335950 (2002-01-01), Kohn
patent: 6456746 (2002-09-01), Freeman
patent: 6470433 (2002-10-01), Prouty et al.
patent: 6487640 (2002-11-01), Lipasti
patent: 6510497 (2003-01-01), Strongin et al.
patent: 6564304 (2003-05-01), Van Hook et al.
patent: 6615326 (2003-09-01), Lin
patent: 2001/0055427 (2001-12-01), Freeman
patent: 2002/0199072 (2002-12-01), Fanning
Kim, Hansoo et al., “High-Performance and Low Power Memory-Interface Architecture for Video Processing Applications,”IEEE Transactions on Circuits and Systems for Video Technology, IEEE Inc., New York, U.S.A., vol. 11, No. 11, Nov. 2001, pp. 1160-1170.
Kim Matthew
Law Office of Andrel D. Popovici, P.C.
Mobilygen Corporation
Patel Hetul
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