Random access memory controller with out of order execution

Details Random access memory controller with out of order execution Random access memory controller with out of order execution

2007-10-09

2007-10-09

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S106000, C711S158000

Reexamination Certificate

active

11498375

ABSTRACT:
A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge in an order that can be different from the order of the corresponding client transactions. The command scheduler may also re-order memory access commands such as read and write. The slicing and out-of-order command scheduling allow a reduction in memory latency. The data transfer to and from clients can be kept in order.

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