Reading extended data burst from memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

Reexamination Certificate

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Details

C711S105000, C711S167000, C365S189040, C365S233100, C365S239000

Reexamination Certificate

active

10425002

ABSTRACT:
A method for reading, from a semiconductor memory, data having a data burst length greater than two includes, beginning at a first time, receiving, on an address bus, a first address part associated with memory cells to be addressed. At a second time that is later than the first time, a read command is placed on a command bus to initiate read access to the first memory cells and a second address part associated with memory cells to be addressed is received on the address bus. Beginning at a third time that is later than the second time, data associated with the first and second address parts is transferred to a data bus.

REFERENCES:
patent: 5828423 (1998-10-01), Serizawa et al.
patent: 6044026 (2000-03-01), Morgan
patent: 6175526 (2001-01-01), Morgan
patent: 6314048 (2001-11-01), Ishikawa
patent: 6333889 (2001-12-01), Arimoto
patent: 6469940 (2002-10-01), Tsuda
Marc Haberland, “Synchrone laufen schneller, Funktionsweise und Technologie synchroner DRAMs,” Elektronik, vol. 19, pp. 113-119 (1995).

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