Reconfigurable data cache controller

Details Reconfigurable data cache controller Reconfigurable data cache controller

1998-02-18

2003-01-14

Yoo, Do Hyun (Department: 2759)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S118000

Reexamination Certificate

active

06507898

ABSTRACT:

An apparatus and method for supplying multiple, separately addressed data items.
FIELD OF THE INVENTION
The present invention relates to the field of data processing systems which use a data cache, and in particular to supplying multiple, separately addressed data items.
BACKGROUND OF THE INVENTION
Data caches in data processing systems are well known and normally provide a small amount of high-speed Random Access Memory (RAM) for storing frequently accessed data. In a conventional data cache, only one item of data is accessed from the cache by the processing unit at a time. In systems where the processing unit requires several items of data from separate tables in memory to perform an operation, it would be advantageous if all the data is supplied to the processing unit in one data packet.
SUMMARY OF THE INVENTION
It is an object of the present invention to ameriolate one or more disadvantages of the prior art.
According to one aspect of the invention there is provided an apparatus for supplying multiple, separately addressed data items from a data table in external memory, said apparatus comprising: a cache memory having n separately addressable memories banks organised as m cache-lines, where n and m are both a plurality; n programmable address generators each coupled to a corresponding one of said n memory banks, the generators using an index to generate multiple addresses to simultaneously retrieve multiple data items from the memory banks, wherein each said generated address includes a tag address and a line address; a tag memory for storing tag addresses of the corresponding lines of the cache memory; a line-valid memory for storing line-valid status of the corresponding lines of the cache memory; n tag comparators, each comparing a tag address of a said generated address with a tag address stored in said tag memory corresponding to the line address of the generated address, and when there is a match and a line-valid status for that line is also asserted a hit signal is generated; and a cache controller for controlling the simultaneous retrieval from the cache memory of the multiple data items in response to said asserted hit signals and for controlling a fetching of one or more said lines containing one or more said data items from the external memory when said associated hit signals are not asserted; and a data organizer for positioning the retrieved data in an output packet.
According to another aspect of the invention there is provided a method for supplying multiple, separately addressed data items from a data table in external memory via a cache memory having n separately addressable memories banks each having m lines, where n and m are both a plurality, the method comprising the steps of: generating multiple addresses, using an index, to simultaneously retrieve multiple data items from the memory banks, wherein each said generated address includes a tag address and a line address; storing tag addresses of the corresponding lines of the cache memory in a tag memory; storing line valid-status of the corresponding lines of the cache memory in a line-valid memory; comparing, for each said generated multiple address, a tag address of the generated address with a tag address stored in said tag memory corresponding to the line address of the generated address, and when there is a match and a line-valid status for that line is also asserted a hit signal is generated; and controlling the simultaneous retrieval from the cache memory of the multiple data items in response to said asserted hit signals and controlling a fetching of one or more said lines containing one or more said data items from the external memory when said associated hit signals are not asserted; and positioning the retrieved data in an output packet.
According to another aspect of the invention there is provided an apparatus for supplying multiple, separately addressed data items from a data table in external memory, said apparatus comprising: a cache memory having n separately addressable memories banks organised as m cache-lines, where each said memory bank consists of m bank-lines, and each said cache-line consists of a said bank-line from each memory bank, and where n and m are both a plurality; n programmable address generators each coupled to a corresponding one of said n memory banks, each generator using an index to generate an external memory address to retrieve a corresponding data item from a said memory bank, wherein each said generated address includes a tag address, a line address and bank address; a tag memory for storing tag addresses of the corresponding cache-lines of the cache memory; a line-valid memory for storing line-valid status of the corresponding cache-lines of the cache memory; n tag comparators, each comparing a tag address of a said generated address with a tag address stored in said tag memory corresponding to the line address of the generated address, and when there is a match and a line-valid status for that line is also asserted a hit signal is generated; and a cache controller for controlling the retrieval from the cache memory of the data items in response to said asserted hit signals and for controlling a fetching of one or more said lines containing one or more said data items from the external memory when said associated hit signals are not asserted; and a data organizer for positioning the retrieved data in an output packet.
According to still another aspect of the invention there is provided an apparatus for supplying multiple, separately addressed data items from a data table in external memory, said apparatus comprising: a cache memory having n separately addressable memories banks organised as m cache-lines, where n and m are both a plurality; n programmable address generators each coupled to a corresponding one of said n memory banks, the generators using an index to generate multiple addresses to simultaneously retrieve multiple data items from the memory banks, wherein each said generated address includes a tag address and a line address; a tag memory for storing tag addresses of the corresponding lines of the cache memory; a line-valid memory for storing line-valid status of the corresponding lines of the cache memory; n tag comparators, each comparing a tag address of a said generated address with a tag address stored in said tag memory corresponding to the line address of the generated address, and when there is a match and a line-valid status for that line is also asserted a hit signal is generated; and a cache controller for controlling the simultaneous retrieval from the cache memory of the multiple data items in response to said asserted hit signals and for controlling a fetching of one or more said lines containing one or more said data items from the external memory when said associated hit signals are not asserted; a data organizer for positioning the retrieved data in an output packet; and an interface for setting a current mode of operation of the apparatus, wherein said address generators generate the multiple addresses in a manner determined by the current mode of operation which is dependent upon the table stored in external memory.
In the following detailed description, the reader's attention is directed, in particular, to
FIGS. 141
to
144
and their associated description without intending to detract from the disclosure of the remainder of the description.
TABLE OF CONTENTS
1.0 BRIEF DESCRIPTION OF THE DRAWINGS
2.0 LIST OF TABLES
3.0 DESCRIPTION OF THE PREFERRED AND OTHER EMBODIMENTS
3.1 General Arrangement of Plural Stream Architecture
3.2 Host/Co-processor Queuing
3.3 Register Description of Co-processor
3.4 Format of Plural Streams
3.5 Determine Current Active Stream
3.6 Fetch Instruction of Current Active Stream
3.7 Decode and Execute Instruction
3.8 Update Registers of Instruction Controller
3.9 Semantics of the Register Access Semaphore
3.10 Instruction Controller
3.11 Description of a Modules Local Register File
3.12 Register Read/Write Handling
3.13 Memory Area Read/Write Handling
3.14 CBus Structure
3.15 Co-processor Data T

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