Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-06-05
2003-04-08
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S151000, C711S154000, C365S194000, C365S233100, C713S401000, C713S600000
Reexamination Certificate
active
06546476
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory devices, and more particularly to dynamic random access memories (DRAM) and a method for controlling DRAMs.
As the technology and speed of processors such as microprocessors and other computer controllers continue to improve, the need for fast and efficient memory devices increases. Often, processors are limited by the speed at which they can retrieve needed data from memory devices. If the data is not available when the processor needs it, the processor stalls until the data is available. This slows the throughput of the system. Consequently, improvements to currently available memory devices are needed to meet the demands of future processors.
Currently available commercial memory devices, such as DRAMs, typically read and write data over a data bus through a bi-directional I/O port. One measure of the efficiency of a memory system is the percentage of time that the data bus is being used. It is desirable that the data bus usage be kept high, so that as much data as possible can be transferred in a given amount of time. If the data bus usage-percentage is low, the cycles in which no data is transferred are lost. The lost cycles are cumulative, and for long data transfers result in the loss of a significant amount of bandwidth on the data bus.
Another factor in determining the efficiency of a memory system is the amount of latency in the system. Latency is the time between the receipt of a read or write instruction and the beginning of data transfer on the data bus. Latency can add delay to the time between when data is requested and when it is received. However, if efficiently managed, this small delay at the beginning of a data transfer becomes insignificant overall.
It is desirable to provide a memory device that operates efficiently. Preferably, the memory device will operate to maximize the overall efficiency of the memory system by making optimum usage of the data bus. Consequently, an improved memory device method of operation of a memory device is needed.
SUMMARY OF THE INVENTION
The present invention provides a memory device and a method of controlling the memory device such that it efficiently transfers data over a data bus. A memory controller or other means adjusts the latency of the write cycle based on the latency of the read cycle. By adjusting the write latency, the usage of the data bus may be optimized, thereby reducing the number of idle time slots when switching between read and write instruction. Preferably, the data from the read and write instructions can be transferred during consecutive data transfer time slots on the data bus with no idle time slots between them.
The specific embodiment discloses a memory device for executing this method. The memory device has several banks of memory arrays that allow concurrent pipelined operation for read and write instructions. A programmable register is provided to allow the latency of the read and write instructions to be optimized.
In accordance with one embodiment of the invention, a method is provided for transferring data on a data bus to and from a memory device, including the steps of issuing a read instruction to the memory device, transferring read data from the memory device after a first time period, issuing a write instruction to the memory device, and delaying a transfer of write data to the memory device for a second time period, wherein the length of the second time period is within two time slots of the length of the first time period.
In accordance with another embodiment, a memory system is provided including a memory device, a command bus for transferring read instructions and write instructions to the memory device, and a data bus for transferring read data from the memory device in response to read instructions, the read data being transferred on the data bus a first time period after the read instruction, and for transferring write data to the memory device in response to write instructions, the write data being transferred on the data bus a second time period after the write instruction. The system further includes a memory controller for controlling the flow of data on the data bus, wherein the length of the second time period is subject to control of a first programmable register
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
patent: 4366538 (1982-12-01), Johnson et al.
patent: 4866675 (1989-09-01), Kawashima
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 4988890 (1991-01-01), Narhi et al.
patent: 5027088 (1991-06-01), Shimizu et al.
patent: 5058051 (1991-10-01), Brooks
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5289431 (1994-02-01), Konishi
patent: 5307314 (1994-04-01), Lee
patent: 5323349 (1994-06-01), Hamade et al.
patent: 5394541 (1995-02-01), Chesley et al.
patent: 5457406 (1995-10-01), Takada et al.
patent: 5490082 (1996-02-01), Rowson
patent: 5500818 (1996-03-01), Chang et al.
patent: 5544124 (1996-08-01), Zagar
patent: 5578940 (1996-11-01), Dillon et al.
patent: 5596731 (1997-01-01), Martinez, Jr. et al.
patent: 5646904 (1997-07-01), Ohno et al.
patent: 5666322 (1997-09-01), Conkle
patent: 5673415 (1997-09-01), Nguyen et al.
patent: 5675298 (1997-10-01), Bhagwan et al.
patent: 5684978 (1997-11-01), Sarma et al.
patent: 5737587 (1998-04-01), Leung et al.
patent: 5768177 (1998-06-01), Sakuragi
patent: 5784582 (1998-07-01), Huhes
patent: 5802586 (1998-09-01), Jones et al.
patent: 5805873 (1998-09-01), Roy
patent: 5813023 (1998-09-01), McLaury
patent: 5813038 (1998-09-01), Thome et al.
patent: 5831925 (1998-11-01), Brown et al.
patent: 5841707 (1998-11-01), Cline et al.
patent: 5845314 (1998-12-01), Ishida
patent: 5917760 (1999-06-01), Millar
patent: 5945886 (1999-08-01), Millar
patent: 6115318 (2000-09-01), Keeth
patent: 6226723 (2001-05-01), Gustavson et al.
Advanced Memory International, Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Moazzami Nasser
Yoo Do Hyun
LandOfFree
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