Rule-based optimizing DRAM controller

Details Rule-based optimizing DRAM controller Rule-based optimizing DRAM controller

1997-05-02

1998-07-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711105, G06F 1200

Patent

active

057784469

ABSTRACT:
A rule-based DRAM controller asserts memory access and control signals (including the CAS, RAS, WE, and address data signals) based upon pre-specified control rules. Certain pre-specified rules, or conditions, are used by the DRAM controller to determine the timing and sequence of the memory accessing and control signals output by the DRAM controller. The control rules for asserting the various memory accessing signals are advantageously implemented as logic within the DRAM controller, while the conditions and qualification for the control rules are provided from various monitoring signals and independently operating timing modules which keep track of the DRAM and controller states. Based upon these rules and conditions, the request inputs to the DRAM controller are interpreted to provide optimum access speed to the DRAM.

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