Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-08-04
2002-05-28
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S103000, C711S108000, C714S006130, C365S200000, C365S230030
Reexamination Certificate
active
06397313
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to the field of non-volatile memory and, more particularly, to sector-based redundancy in a nonvolatile memory array configured in a dual bank architecture that is capable of performing simultaneous operation.
BACKGROUND
Computers, personal digital assistants, cellular telephones and other electronic systems and devices typically include processors and memory. The memory will be used to store instructions (typically in the form of computer programs) to be executed and/or data to be operated on by the processors to achieve the functionality of the device. In some applications, the systems and devices may require that the instructions and/or data be retained in some form of permanent
on-volatile storage medium so that the information is not lost when the device is turned off or power is removed. Exemplary applications include computer BIOS storage and diskless handheld computing devices such as personal digital assistants.
One type of non-volatile memory that can be used is flash Electrically Erasable Programmable Read Only Memory (“EEPROM”) which is commonly referred to as a flash memory. Flash memory is a form of non-volatile storage, which uses a memory cell design with a floating gate. Voltages are applied to the memory cell inputs to program/store charge on the floating gate or to erase/remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove electronic charge from the floating gate. Erasing a cell sets the logical value of the cell to “1” while programming the cell sets the logical value to “0”.
Flash memory is typically divided logically into blocks called “sectors” where each sector contains a portion of the total bytes of data storage available. For example, a typical flash memory may have 32 megabits of total storage and be logically broken down into 64 sectors, each sector containing 64 kilobytes of data (one byte being equal to eight bits). This arrangement allows for the option of erasure of one sector at a time in addition to bulk erasure of the entire flash memory. Bye-bye-byte erasure is currently not possible although, depending on the implementation, data in the flash memory can be programmed and read byte by byte (or sometimes word by word, where a word equals four bytes).
Flash memory is manufactured to form rows and columns of memory cells that result in a memory array. The memory array is accessed by a row decoder (a wordline decoder) and a column decoder (a bitline decoder) that are used to address a particular memory cell or row of memory cells in the memory array. A sense amplifier is built into the flash memory for sensing the logic value of the selected memory cell(s) when addressed by the row decoder and column decoder. In recent years, the density of the memory array on a flash memory has increased dramatically. As the density of the memory array on a flash memory increases, it becomes significantly more difficult to produce perfect flash memory. During fabrication of the flash memory, it is common for the memory array to include one or more defective memory cells due to short circuits, open circuits and other operational defects. In an effort to improve production yields and flash memory reliability, spare or redundant memory cells are typically included on the flash memory so as to allow for repairing or replacing the defective memory cells in the memory array.
The flash memory is generally first tested to determine whether it operates properly while it is part of a semiconductor wafer joined with other flash memory. If a faulty area containing defective memory cells is located, redundant memory cells are substituted for the defective memory cells in the faulty area. Typically, circuitry is required for selectively deactivating the defective memory cells when repair is desired and for activating the redundant memory cells to effect the substitution. Since the flash memory is divided into sectors, the redundant memory cells are associated with one or more sectors such that defective memory cells within a sector are replaced by redundant memory cells associated with that particular sector.
The redundant memory cells and the memory cells are contained in a plurality of redundant blocks with each redundant block containing a plurality of the sectors. To allow repair of the defective memory cells by the redundant memory cells; an address of a column of defective memory cells is cross-referenced by the flash memory with the location of a column of redundant memory cells. The cross-referencing is accomplished by assigning an address storage location to the location of the column of redundant memory cells.
The address storage location is also assigned to a particular redundant block location. Column addresses of defective columns of memory cells that are stored in the particular address storage locations are located within the assigned redundant block location. The defective memory cells are repaired by the column of redundant memory cells that are assigned to the particular address storage location. The column address of the defective memory cells is stored in the address storage location and later compared against a column address of memory cells that are active within the flash memory during operation. If the addresses match, replacement of the active column of memory cells with a column of redundant memory cells occurs.
A problem arises when the redundant blocks within the flash memory can be selectively configured into different locations. Since the address storage locations are assigned to the redundant block locations, additional address storage locations are required to account for the different possible redundant block locations. However, only the address storage locations where the redundant block is located will be used while the additional address storage remain idle.
The increased circuitry caused by the increase in address storage locations reduces the area available for flash memory cells as well as increases the power consumed by the flash memory. In addition, in the prior art only one column of defective memory cells can be repaired at a time. Therefore, if the flash memory is capable of simultaneously performing tasks in redundant blocks in different locations, the redundancy may slow down operation of the flash memory while a redundant block in one location waits for a redundant block in the other location to complete a repair.
SUMMARY
By way of introduction, this invention relates generally to floating gate memory devices such as an array of flash electrically erasable programmable read-only memory (EEPROM) cells with sector-based redundancy. More particularly, the present invention relates to sector-based redundancy for an array of flash EEPROM cells in a sliding bank configuration that is referred to as a simultaneous operation flash memory.
The simultaneous operation flash memory is divided into an upper bank and a sliding lower bank and provides for reading in one bank while simultaneously performing a program or erase operation in the other bank. The simultaneous operation flash memory uses a sliding bank architecture that allows the user to vary the megabit density of the upper bank and the sliding lower bank by designating whether a plurality of redundant blocks (b
0
-b
7
) will be located in the upper bank or the sliding lower bank. Within each redundant block (b
0
-b
7
) is a plurality of sectors containing a plurality of columns of memory cells and a plurality of rows of memory cells that form the memory array. The plurality of sectors also include a plurality of columns and rows of redundant memory cells.
The presently preferred simultaneous operation flash memory includes sector-based redundancy that is capable of repairing a column of memory cells that is defective in the upper bank and repairing a column of memory cells that is defective in the sliding lower bank at the same time. T
Kasa Yasushi
Wang Guowei
Portka Gary J.
Wagner , Murabito & Hao LLP
Yoo Do Hyun
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