Versatile multiplexer-structures in programmable logic using...
Versatile multiplexer-structures in programmable logic using...
Vertex based layout pattern (VEP): a method and apparatus...
Via density change to improve wafer surface planarity
Via enclosure rule check in a multi-wide object class design...
Via redundancy based on subnet timing information, target...
Via structure to improve routing of wires within an...
Via/BSM pattern optimization to reduce DC gradients and pin...
Video processing architecture definition by function graph...
Virtual component having a detachable...
Virtual data representation through selective bidirectional...
Virtual logic system for solving satisfiability problems...
Virtual path for interconnect fabric using bandwidth process
Virtual shape based parameterized cell
Virtual tree-based netlist model and method of delay...
Visual analysis and verification system using advanced tools
Visualizing hardware cost in high level modeling systems
Visualizing hardware cost in high level modeling systems
VLSI artwork legalization for hierarchical designs with...
VLSI artwork legalization for hierarchical designs with...