Visualizing hardware cost in high level modeling systems

Details Visualizing hardware cost in high level modeling systems Visualizing hardware cost in high level modeling systems

2005-08-03

2008-10-28

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S020000

Reexamination Certificate

active

07444610

ABSTRACT:
Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the circuit design having at least one visual characteristic which can be varied according to the hardware cost information.

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