Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-06-14
2011-06-14
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S112000, C716S135000
Reexamination Certificate
active
07962881
ABSTRACT:
In consideration for the fact that a connection on the upper layers of an integrated circuit needs to access a lower layer to connect to, e.g., a transistor, at least one via on each layer is required below the top layer used by a connection for each pin. The vias (i.e., the connection structures between wiring planes within an integrated circuit) are arranged such that the number of wiring resources blocked on the lower layers is reduced. Various rules govern which vias are chosen. The main characteristic is to elect only a certain number of wiring channels appropriate for the vias on a single layer and then apply an optimization within the restricted elected wiring channels on that layer to select the most appropriate vias.
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Buehler Markus T.
Gangwar Ankit
Koehl Juergen
Mishra Arun K.
Cai Yuanmin
Cantor & Colburn LLP
International Business Machines - Corporation
Levin Naum
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